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ARM: dts: exynos: move exynos-bus nodes out of soc in Exynos4412
The soc node is supposed to have only device nodes with MMIO addresses,
as reported by dtc W=1:
exynos4412.dtsi:407.20-413.5:
Warning (simple_bus_reg): /soc/bus-acp: missing or empty reg/ranges property
and dtbs_check:
exynos4412-i9300.dtb: soc: bus-acp:
{'compatible': ['samsung,exynos-bus'], 'clocks': [[7, 456]], 'clock-names': ['bus'], 'operating-points-v2': [[132]], 'status': ['okay'], 'devfreq': [[117]]} should not be valid under {'type': 'object'}
Move the bus nodes and their OPP tables out of SoC to fix this.
Re-order them alphabetically while moving and put some of the OPP tables
in device nodes (if they are not shared).
Link: https://lore.kernel.org/r/20230125094513.155063-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Krzysztof Kozlowski
parent
09dd37396a
commit
adf8238ef4
1 changed files with 175 additions and 176 deletions
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@ -31,6 +31,134 @@ aliases {
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mshc0 = &mshc_0;
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};
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bus_acp: bus-acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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bus_acp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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};
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};
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};
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bus_c2c: bus-c2c {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_C2C>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc: bus-dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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samsung,data-clock-ratio = <4>;
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#interconnect-cells = <0>;
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status = "disabled";
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};
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bus_display: bus-display {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_display_opp_table>;
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interconnects = <&bus_leftbus &bus_dmc>;
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#interconnect-cells = <0>;
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status = "disabled";
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bus_display_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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};
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bus_fsys: bus-fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK133>;
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clock-names = "bus";
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operating-points-v2 = <&bus_fsys_opp_table>;
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status = "disabled";
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bus_fsys_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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};
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};
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bus_leftbus: bus-leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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interconnects = <&bus_dmc>;
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#interconnect-cells = <0>;
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status = "disabled";
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};
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bus_mfc: bus-mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_peri: bus-peri {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peri_opp_table>;
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status = "disabled";
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bus_peri_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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};
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};
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bus_rightbus: bus-rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -171,6 +299,53 @@ cpu0_opp_1500: opp-1500000000 {
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};
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};
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bus_dmc_opp_table: opp-table-1 {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <900000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <900000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <900000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <950000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1050000>;
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opp-suspend;
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};
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};
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bus_leftbus_opp_table: opp-table-2 {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <900000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <925000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <950000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <1000000>;
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opp-suspend;
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};
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};
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soc: soc {
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@ -393,182 +568,6 @@ sysmmu_fimc_lite1: sysmmu@123c0000 {
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<&isp_clock CLK_ISP_FIMC_LITE1>;
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#iommu-cells = <0>;
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};
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bus_dmc: bus-dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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samsung,data-clock-ratio = <4>;
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#interconnect-cells = <0>;
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status = "disabled";
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};
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bus_acp: bus-acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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};
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bus_c2c: bus-c2c {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_C2C>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp-table-1 {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <900000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <900000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <900000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <950000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1050000>;
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opp-suspend;
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};
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};
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bus_acp_opp_table: opp-table-2 {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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};
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};
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bus_leftbus: bus-leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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interconnects = <&bus_dmc>;
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#interconnect-cells = <0>;
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status = "disabled";
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};
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bus_rightbus: bus-rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_display: bus-display {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_display_opp_table>;
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interconnects = <&bus_leftbus &bus_dmc>;
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#interconnect-cells = <0>;
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status = "disabled";
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};
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bus_fsys: bus-fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK133>;
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clock-names = "bus";
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operating-points-v2 = <&bus_fsys_opp_table>;
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status = "disabled";
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};
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bus_peri: bus-peri {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peri_opp_table>;
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status = "disabled";
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};
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bus_mfc: bus-mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_leftbus_opp_table: opp-table-3 {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <900000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <925000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <950000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <1000000>;
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opp-suspend;
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};
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};
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bus_display_opp_table: opp-table-4 {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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bus_fsys_opp_table: opp-table-5 {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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};
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bus_peri_opp_table: opp-table-6 {
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compatible = "operating-points-v2";
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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};
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};
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};
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