mirrors/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2025-11-04 10:40:15 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions

irqchip: mips-gic: Clean up mti, reserved-cpu-vectors handling

Browse source 
When parsing mti,reserved-cpu-vectors we generate a mask of all bits
that have been declared reserved, the loop through starting from bit 2
to find one that isn't reserved (ie. is zero).

This patch accomplishes the same task more simply by:

  - Inititialising the reserved mask to 0x3 (ie. the 2 software
    interrupts). This means we don't need to skip them later as the loop
    previously has.

  - Replacing the loop checking for zero bits with find_first_zero_bit,
    which fits our needs now that the 2 software interrupts are marked
    reserved. This requires that the type of reserved is changed to
    unsigned long so that it's suitable for use with bitmap functions.

  - Replacing the magic number 8 with the hamming weight of the ST0_IM
    field - ie. the number of bits that a MIPS CPU has for interrupt
    inputs. This is still a compile-time constant 8, but makes it
    clearer why it's 8.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17054/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2017-08-12 21:36:44 -07:00 committed by Ralf Baechle
parent 7778c4b27c
commit b2b2e584ce
1 changed files with 7 additions and 7 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

14
drivers/irqchip/irq-mips-gic.c
View file

@ -636,21 +636,21 @@ static const struct irq_domain_ops gic_ipi_domain_ops = {
static int __init gic_of_init(struct device_node *node,
struct device_node *parent)
{
unsigned int cpu_vec, i, j, reserved, gicconfig, cpu, v[2];
unsigned int cpu_vec, i, j, gicconfig, cpu, v[2];
unsigned long reserved;
phys_addr_t gic_base;
struct resource res;
size_t gic_len;
/* Find the first available CPU vector. */
i = reserved = 0;
i = 0;
reserved = (C_SW0 | C_SW1) >> __fls(C_SW0);
while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
i++, &cpu_vec))
reserved |= BIT(cpu_vec);
for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
if (!(reserved & BIT(cpu_vec)))
break;
}
if (cpu_vec == 8) {
cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
if (cpu_vec == hweight_long(ST0_IM)) {
pr_err("No CPU vectors available for GIC\n");
return -ENODEV;
}