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i2c: designware: Set IRQF_NO_SUSPEND flag for all BYT and CHT controllers

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On some Cherry Trail systems the GPU ACPI fwnode has power-resources which
point to the PMIC, which is connected over a LPSS I2C controller. The GPU
is a PCI device and PCI devices are powered-on at the resume_noirq resume
phase.

Since the GPU power-resources need the I2C controller, recent acpi_lpss.c
changes now also power-up the LPSS I2C controllers on BYT and CHT devices
in the resume_noirq resume phase. But during this phase the IRQ of the
controller is disabled leading to these errors:

 i2c_designware 808622C1:06: controller timed out
 ACPI Error: AE_ERROR, Returned by Handler for [UserDefinedRegion]
 ACPI Error: Method parse/execution failed \_SB.P18W._ON, AE_ERROR
 video LNXVIDEO:00: Failed to change power state to D0

This commit makes the i2c-designware controller set the IRQF_NO_SUSPEND
flag when requesting the interrupt on BYT and CHT devices, so that the IRQ
is left enabled during the noirq phase, fixing this.

Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Hans de Goede 2018-10-06 10:25:39 +02:00 committed by Wolfram Sang
parent cc52612ec0
commit b30f2f6556
3 changed files with 4 additions and 3 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/i2c/busses/i2c-designware-core.h
View file

@ -278,6 +278,7 @@ struct dw_i2c_dev {
#define ACCESS_SWAP 0x00000001 #define ACCESS_SWAP 0x00000001
#define ACCESS_16BIT 0x00000002 #define ACCESS_16BIT 0x00000002
#define ACCESS_INTR_MASK 0x00000004 #define ACCESS_INTR_MASK 0x00000004
#define ACCESS_NO_IRQ_SUSPEND 0x00000008
#define MODEL_CHERRYTRAIL 0x00000100 #define MODEL_CHERRYTRAIL 0x00000100
#define MODEL_MSCC_OCELOT 0x00000200 #define MODEL_MSCC_OCELOT 0x00000200

2
drivers/i2c/busses/i2c-designware-master.c
View file

@ -707,7 +707,7 @@ int i2c_dw_probe(struct dw_i2c_dev *dev)
adap->dev.parent = dev->dev; adap->dev.parent = dev->dev;
i2c_set_adapdata(adap, dev); i2c_set_adapdata(adap, dev);
if (dev->shared_with_punit) { if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
irq_flags = IRQF_NO_SUSPEND; irq_flags = IRQF_NO_SUSPEND;
} else { } else {
irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;

4
drivers/i2c/busses/i2c-designware-platdrv.c
View file

@ -123,8 +123,8 @@ static const struct acpi_device_id dw_i2c_acpi_match[] = {
{ "INT33C3", 0 }, { "INT33C3", 0 },
{ "INT3432", 0 }, { "INT3432", 0 },
{ "INT3433", 0 }, { "INT3433", 0 },
{ "80860F41", 0 }, { "80860F41", ACCESS_NO_IRQ_SUSPEND },
{ "808622C1", MODEL_CHERRYTRAIL }, { "808622C1", ACCESS_NO_IRQ_SUSPEND | MODEL_CHERRYTRAIL },
{ "AMD0010", ACCESS_INTR_MASK }, { "AMD0010", ACCESS_INTR_MASK },
{ "AMDI0010", ACCESS_INTR_MASK }, { "AMDI0010", ACCESS_INTR_MASK },
{ "AMDI0510", 0 }, { "AMDI0510", 0 },