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drm amdgpu: SI UVD v3_1 (v2)
Implement SI UVD. The SI UVD firmware requires validation. v2: squash in missing brace fix (Colin Ian King) Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sonny Jiang
Alex Deucher
parent
2282b4186d
commit
b38f3e80ec
2 changed files with 822 additions and 0 deletions
793
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
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793
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Sonny Jiang <sonny.jiang@amd.com>
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_uvd.h"
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#include "sid.h"
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#include "uvd/uvd_3_1_d.h"
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#include "uvd/uvd_3_1_sh_mask.h"
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#include "oss/oss_1_0_d.h"
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#include "oss/oss_1_0_sh_mask.h"
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/**
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* uvd_v3_1_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint64_t uvd_v3_1_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32(mmUVD_RBC_RB_RPTR);
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}
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/**
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* uvd_v3_1_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint64_t uvd_v3_1_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32(mmUVD_RBC_RB_WPTR);
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}
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/**
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* uvd_v3_1_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void uvd_v3_1_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
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}
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/**
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* uvd_v3_1_ring_emit_ib - execute indirect buffer
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*
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* @ring: amdgpu_ring pointer
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* @ib: indirect buffer to execute
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*
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* Write ring commands to execute the indirect buffer
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*/
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static void uvd_v3_1_ring_emit_ib(struct amdgpu_ring *ring,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib,
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uint32_t flags)
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{
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amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
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amdgpu_ring_write(ring, ib->gpu_addr);
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amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
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amdgpu_ring_write(ring, ib->length_dw);
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}
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/**
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* uvd_v3_1_ring_emit_fence - emit an fence & trap command
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*
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* @ring: amdgpu_ring pointer
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* @fence: fence to emit
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*
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* Write a fence and a trap command to the ring.
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*/
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static void uvd_v3_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
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unsigned flags)
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{
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
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amdgpu_ring_write(ring, addr & 0xffffffff);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
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amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
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amdgpu_ring_write(ring, 2);
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}
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/**
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* uvd_v3_1_ring_test_ring - register write test
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*
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* @ring: amdgpu_ring pointer
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*
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* Test if we can successfully write to the context register
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*/
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static int uvd_v3_1_ring_test_ring(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 3);
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if (r)
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return r;
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amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(mmUVD_CONTEXT_ID);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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return r;
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}
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static void uvd_v3_1_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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{
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int i;
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WARN_ON(ring->wptr % 2 || count % 2);
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for (i = 0; i < count / 2; i++) {
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amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
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amdgpu_ring_write(ring, 0);
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}
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}
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static const struct amdgpu_ring_funcs uvd_v3_1_ring_funcs = {
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.type = AMDGPU_RING_TYPE_UVD,
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.align_mask = 0xf,
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.support_64bit_ptrs = false,
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.no_user_fence = true,
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.get_rptr = uvd_v3_1_ring_get_rptr,
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.get_wptr = uvd_v3_1_ring_get_wptr,
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.set_wptr = uvd_v3_1_ring_set_wptr,
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.parse_cs = amdgpu_uvd_ring_parse_cs,
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.emit_frame_size =
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14, /* uvd_v3_1_ring_emit_fence x1 no user fence */
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.emit_ib_size = 4, /* uvd_v3_1_ring_emit_ib */
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.emit_ib = uvd_v3_1_ring_emit_ib,
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.emit_fence = uvd_v3_1_ring_emit_fence,
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.test_ring = uvd_v3_1_ring_test_ring,
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.test_ib = amdgpu_uvd_ring_test_ib,
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.insert_nop = uvd_v3_1_ring_insert_nop,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_uvd_ring_begin_use,
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.end_use = amdgpu_uvd_ring_end_use,
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};
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static void uvd_v3_1_set_ring_funcs(struct amdgpu_device *adev)
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{
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adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;
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}
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static void uvd_v3_1_set_dcm(struct amdgpu_device *adev,
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bool sw_mode)
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{
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u32 tmp, tmp2;
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WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
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tmp = RREG32(mmUVD_CGC_CTRL);
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tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
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tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
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(1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
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(4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
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if (sw_mode) {
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tmp &= ~0x7ffff800;
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tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
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UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
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(7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
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} else {
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tmp |= 0x7ffff800;
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tmp2 = 0;
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}
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WREG32(mmUVD_CGC_CTRL, tmp);
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WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
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}
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/**
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* uvd_v3_1_mc_resume - memory controller programming
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*
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* @adev: amdgpu_device pointer
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*
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* Let the UVD memory controller know it's offsets
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*/
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static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
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{
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uint64_t addr;
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uint32_t size;
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/* programm the VCPU memory controller bits 0-27 */
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addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
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size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
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WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
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WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = AMDGPU_UVD_HEAP_SIZE >> 3;
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WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
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WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = (AMDGPU_UVD_STACK_SIZE +
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(AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
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WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
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WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
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/* bits 28-31 */
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addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
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WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
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/* bits 32-39 */
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addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
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WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
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WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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}
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/**
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* uvd_v3_1_fw_validate - FW validation operation
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*
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* @adev: amdgpu_device pointer
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*
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* Initialate and check UVD validation.
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*/
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static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
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{
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void *ptr;
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uint32_t ucode_len, i;
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uint32_t keysel;
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ptr = adev->uvd.inst[0].cpu_addr;
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ptr += 192 + 16;
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memcpy(&ucode_len, ptr, 4);
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ptr += ucode_len;
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memcpy(&keysel, ptr, 4);
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WREG32(mmUVD_FW_START, keysel);
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for (i = 0; i < 10; ++i) {
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mdelay(10);
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if (RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__DONE_MASK)
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break;
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}
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if (i == 10)
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return -ETIMEDOUT;
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if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__PASS_MASK))
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return -EINVAL;
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for (i = 0; i < 10; ++i) {
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mdelay(10);
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if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__BUSY_MASK))
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break;
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}
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if (i == 10)
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return -ETIMEDOUT;
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return 0;
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}
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/**
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* uvd_v3_1_start - start UVD block
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*
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* @adev: amdgpu_device pointer
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*
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* Setup and start the UVD block
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*/
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static int uvd_v3_1_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = &adev->uvd.inst->ring;
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uint32_t rb_bufsz;
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int i, j, r;
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u32 tmp;
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/* disable byte swapping */
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u32 lmi_swap_cntl = 0;
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u32 mp_swap_cntl = 0;
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/* set uvd busy */
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WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
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uvd_v3_1_set_dcm(adev, true);
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WREG32(mmUVD_CGC_GATE, 0);
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/* take UVD block out of reset */
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WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
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mdelay(5);
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/* enable VCPU clock */
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WREG32(mmUVD_VCPU_CNTL, 1 << 9);
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/* disable interupt */
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||||||
|
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
|
||||||
|
|
||||||
|
#ifdef __BIG_ENDIAN
|
||||||
|
/* swap (8 in 32) RB and IB */
|
||||||
|
lmi_swap_cntl = 0xa;
|
||||||
|
mp_swap_cntl = 0;
|
||||||
|
#endif
|
||||||
|
WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
|
||||||
|
WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
|
||||||
|
|
||||||
|
/* initialize UVD memory controller */
|
||||||
|
WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
|
||||||
|
(1 << 21) | (1 << 9) | (1 << 20));
|
||||||
|
|
||||||
|
tmp = RREG32(mmUVD_MPC_CNTL);
|
||||||
|
WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
|
||||||
|
|
||||||
|
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
|
||||||
|
WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
|
||||||
|
WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
|
||||||
|
WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
|
||||||
|
WREG32(mmUVD_MPC_SET_ALU, 0);
|
||||||
|
WREG32(mmUVD_MPC_SET_MUX, 0x88);
|
||||||
|
|
||||||
|
tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
|
||||||
|
WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
|
||||||
|
|
||||||
|
/* enable UMC */
|
||||||
|
WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
|
||||||
|
|
||||||
|
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
|
||||||
|
|
||||||
|
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
|
||||||
|
|
||||||
|
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
|
||||||
|
|
||||||
|
mdelay(10);
|
||||||
|
|
||||||
|
for (i = 0; i < 10; ++i) {
|
||||||
|
uint32_t status;
|
||||||
|
for (j = 0; j < 100; ++j) {
|
||||||
|
status = RREG32(mmUVD_STATUS);
|
||||||
|
if (status & 2)
|
||||||
|
break;
|
||||||
|
mdelay(10);
|
||||||
|
}
|
||||||
|
r = 0;
|
||||||
|
if (status & 2)
|
||||||
|
break;
|
||||||
|
|
||||||
|
DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
|
||||||
|
WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
|
||||||
|
~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
|
||||||
|
mdelay(10);
|
||||||
|
WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
|
||||||
|
mdelay(10);
|
||||||
|
r = -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (r) {
|
||||||
|
DRM_ERROR("UVD not responding, giving up!!!\n");
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* enable interupt */
|
||||||
|
WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
|
||||||
|
|
||||||
|
WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
|
||||||
|
|
||||||
|
/* force RBC into idle state */
|
||||||
|
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
|
||||||
|
|
||||||
|
/* Set the write pointer delay */
|
||||||
|
WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
|
||||||
|
|
||||||
|
/* programm the 4GB memory segment for rptr and ring buffer */
|
||||||
|
WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
|
||||||
|
(0x7 << 16) | (0x1 << 31));
|
||||||
|
|
||||||
|
/* Initialize the ring buffer's read and write pointers */
|
||||||
|
WREG32(mmUVD_RBC_RB_RPTR, 0x0);
|
||||||
|
|
||||||
|
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
|
||||||
|
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
|
||||||
|
|
||||||
|
/* set the ring address */
|
||||||
|
WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
|
||||||
|
|
||||||
|
/* Set ring buffer size */
|
||||||
|
rb_bufsz = order_base_2(ring->ring_size);
|
||||||
|
rb_bufsz = (0x1 << 8) | rb_bufsz;
|
||||||
|
WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* uvd_v3_1_stop - stop UVD block
|
||||||
|
*
|
||||||
|
* @adev: amdgpu_device pointer
|
||||||
|
*
|
||||||
|
* stop the UVD block
|
||||||
|
*/
|
||||||
|
static void uvd_v3_1_stop(struct amdgpu_device *adev)
|
||||||
|
{
|
||||||
|
uint32_t i, j;
|
||||||
|
uint32_t status;
|
||||||
|
|
||||||
|
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
|
||||||
|
|
||||||
|
for (i = 0; i < 10; ++i) {
|
||||||
|
for (j = 0; j < 100; ++j) {
|
||||||
|
status = RREG32(mmUVD_STATUS);
|
||||||
|
if (status & 2)
|
||||||
|
break;
|
||||||
|
mdelay(1);
|
||||||
|
}
|
||||||
|
if (status & 2)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < 10; ++i) {
|
||||||
|
for (j = 0; j < 100; ++j) {
|
||||||
|
status = RREG32(mmUVD_LMI_STATUS);
|
||||||
|
if (status & 0xf)
|
||||||
|
break;
|
||||||
|
mdelay(1);
|
||||||
|
}
|
||||||
|
if (status & 0xf)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Stall UMC and register bus before resetting VCPU */
|
||||||
|
WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
|
||||||
|
|
||||||
|
for (i = 0; i < 10; ++i) {
|
||||||
|
for (j = 0; j < 100; ++j) {
|
||||||
|
status = RREG32(mmUVD_LMI_STATUS);
|
||||||
|
if (status & 0x240)
|
||||||
|
break;
|
||||||
|
mdelay(1);
|
||||||
|
}
|
||||||
|
if (status & 0x240)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
WREG32_P(0x3D49, 0, ~(1 << 2));
|
||||||
|
|
||||||
|
WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
|
||||||
|
|
||||||
|
/* put LMI, VCPU, RBC etc... into reset */
|
||||||
|
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
|
||||||
|
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
|
||||||
|
UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
|
||||||
|
|
||||||
|
WREG32(mmUVD_STATUS, 0);
|
||||||
|
|
||||||
|
uvd_v3_1_set_dcm(adev, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_set_interrupt_state(struct amdgpu_device *adev,
|
||||||
|
struct amdgpu_irq_src *source,
|
||||||
|
unsigned type,
|
||||||
|
enum amdgpu_interrupt_state state)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_process_interrupt(struct amdgpu_device *adev,
|
||||||
|
struct amdgpu_irq_src *source,
|
||||||
|
struct amdgpu_iv_entry *entry)
|
||||||
|
{
|
||||||
|
DRM_DEBUG("IH: UVD TRAP\n");
|
||||||
|
amdgpu_fence_process(&adev->uvd.inst->ring);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static const struct amdgpu_irq_src_funcs uvd_v3_1_irq_funcs = {
|
||||||
|
.set = uvd_v3_1_set_interrupt_state,
|
||||||
|
.process = uvd_v3_1_process_interrupt,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void uvd_v3_1_set_irq_funcs(struct amdgpu_device *adev)
|
||||||
|
{
|
||||||
|
adev->uvd.inst->irq.num_types = 1;
|
||||||
|
adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static int uvd_v3_1_early_init(void *handle)
|
||||||
|
{
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
adev->uvd.num_uvd_inst = 1;
|
||||||
|
|
||||||
|
uvd_v3_1_set_ring_funcs(adev);
|
||||||
|
uvd_v3_1_set_irq_funcs(adev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_sw_init(void *handle)
|
||||||
|
{
|
||||||
|
struct amdgpu_ring *ring;
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
int r;
|
||||||
|
|
||||||
|
/* UVD TRAP */
|
||||||
|
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
r = amdgpu_uvd_sw_init(adev);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
ring = &adev->uvd.inst->ring;
|
||||||
|
sprintf(ring->name, "uvd");
|
||||||
|
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
|
||||||
|
AMDGPU_RING_PRIO_DEFAULT);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
r = amdgpu_uvd_resume(adev);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
r = amdgpu_uvd_entity_init(adev);
|
||||||
|
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_sw_fini(void *handle)
|
||||||
|
{
|
||||||
|
int r;
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
r = amdgpu_uvd_suspend(adev);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
return amdgpu_uvd_sw_fini(adev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void uvd_v3_1_enable_mgcg(struct amdgpu_device *adev,
|
||||||
|
bool enable)
|
||||||
|
{
|
||||||
|
u32 orig, data;
|
||||||
|
|
||||||
|
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
|
||||||
|
data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
|
||||||
|
data |= 0x3fff;
|
||||||
|
WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
|
||||||
|
|
||||||
|
orig = data = RREG32(mmUVD_CGC_CTRL);
|
||||||
|
data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
|
||||||
|
if (orig != data)
|
||||||
|
WREG32(mmUVD_CGC_CTRL, data);
|
||||||
|
} else {
|
||||||
|
data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
|
||||||
|
data &= ~0x3fff;
|
||||||
|
WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
|
||||||
|
|
||||||
|
orig = data = RREG32(mmUVD_CGC_CTRL);
|
||||||
|
data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
|
||||||
|
if (orig != data)
|
||||||
|
WREG32(mmUVD_CGC_CTRL, data);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* uvd_v3_1_hw_init - start and test UVD block
|
||||||
|
*
|
||||||
|
* @adev: amdgpu_device pointer
|
||||||
|
*
|
||||||
|
* Initialize the hardware, boot up the VCPU and do some testing
|
||||||
|
*/
|
||||||
|
static int uvd_v3_1_hw_init(void *handle)
|
||||||
|
{
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
|
||||||
|
uint32_t tmp;
|
||||||
|
int r;
|
||||||
|
|
||||||
|
uvd_v3_1_mc_resume(adev);
|
||||||
|
|
||||||
|
r = uvd_v3_1_fw_validate(adev);
|
||||||
|
if (r) {
|
||||||
|
DRM_ERROR("amdgpu: UVD Firmware validate fail (%d).\n", r);
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
uvd_v3_1_enable_mgcg(adev, true);
|
||||||
|
amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
|
||||||
|
|
||||||
|
uvd_v3_1_start(adev);
|
||||||
|
|
||||||
|
r = amdgpu_ring_test_helper(ring);
|
||||||
|
if (r) {
|
||||||
|
DRM_ERROR("amdgpu: UVD ring test fail (%d).\n", r);
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
|
||||||
|
r = amdgpu_ring_alloc(ring, 10);
|
||||||
|
if (r) {
|
||||||
|
DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
|
||||||
|
amdgpu_ring_write(ring, tmp);
|
||||||
|
amdgpu_ring_write(ring, 0xFFFFF);
|
||||||
|
|
||||||
|
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
|
||||||
|
amdgpu_ring_write(ring, tmp);
|
||||||
|
amdgpu_ring_write(ring, 0xFFFFF);
|
||||||
|
|
||||||
|
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
|
||||||
|
amdgpu_ring_write(ring, tmp);
|
||||||
|
amdgpu_ring_write(ring, 0xFFFFF);
|
||||||
|
|
||||||
|
/* Clear timeout status bits */
|
||||||
|
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
|
||||||
|
amdgpu_ring_write(ring, 0x8);
|
||||||
|
|
||||||
|
amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
|
||||||
|
amdgpu_ring_write(ring, 3);
|
||||||
|
|
||||||
|
amdgpu_ring_commit(ring);
|
||||||
|
|
||||||
|
done:
|
||||||
|
if (!r)
|
||||||
|
DRM_INFO("UVD initialized successfully.\n");
|
||||||
|
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* uvd_v3_1_hw_fini - stop the hardware block
|
||||||
|
*
|
||||||
|
* @adev: amdgpu_device pointer
|
||||||
|
*
|
||||||
|
* Stop the UVD block, mark ring as not ready any more
|
||||||
|
*/
|
||||||
|
static int uvd_v3_1_hw_fini(void *handle)
|
||||||
|
{
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
if (RREG32(mmUVD_STATUS) != 0)
|
||||||
|
uvd_v3_1_stop(adev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_suspend(void *handle)
|
||||||
|
{
|
||||||
|
int r;
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
r = uvd_v3_1_hw_fini(adev);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
return amdgpu_uvd_suspend(adev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_resume(void *handle)
|
||||||
|
{
|
||||||
|
int r;
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
r = amdgpu_uvd_resume(adev);
|
||||||
|
if (r)
|
||||||
|
return r;
|
||||||
|
|
||||||
|
return uvd_v3_1_hw_init(adev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool uvd_v3_1_is_idle(void *handle)
|
||||||
|
{
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_wait_for_idle(void *handle)
|
||||||
|
{
|
||||||
|
unsigned i;
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
for (i = 0; i < adev->usec_timeout; i++) {
|
||||||
|
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_soft_reset(void *handle)
|
||||||
|
{
|
||||||
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
|
uvd_v3_1_stop(adev);
|
||||||
|
|
||||||
|
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
|
||||||
|
~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
|
||||||
|
mdelay(5);
|
||||||
|
|
||||||
|
return uvd_v3_1_start(adev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_set_clockgating_state(void *handle,
|
||||||
|
enum amd_clockgating_state state)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int uvd_v3_1_set_powergating_state(void *handle,
|
||||||
|
enum amd_powergating_state state)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
|
||||||
|
.name = "uvd_v3_1",
|
||||||
|
.early_init = uvd_v3_1_early_init,
|
||||||
|
.late_init = NULL,
|
||||||
|
.sw_init = uvd_v3_1_sw_init,
|
||||||
|
.sw_fini = uvd_v3_1_sw_fini,
|
||||||
|
.hw_init = uvd_v3_1_hw_init,
|
||||||
|
.hw_fini = uvd_v3_1_hw_fini,
|
||||||
|
.suspend = uvd_v3_1_suspend,
|
||||||
|
.resume = uvd_v3_1_resume,
|
||||||
|
.is_idle = uvd_v3_1_is_idle,
|
||||||
|
.wait_for_idle = uvd_v3_1_wait_for_idle,
|
||||||
|
.soft_reset = uvd_v3_1_soft_reset,
|
||||||
|
.set_clockgating_state = uvd_v3_1_set_clockgating_state,
|
||||||
|
.set_powergating_state = uvd_v3_1_set_powergating_state,
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct amdgpu_ip_block_version uvd_v3_1_ip_block =
|
||||||
|
{
|
||||||
|
.type = AMD_IP_BLOCK_TYPE_UVD,
|
||||||
|
.major = 3,
|
||||||
|
.minor = 1,
|
||||||
|
.rev = 0,
|
||||||
|
.funcs = &uvd_v3_1_ip_funcs,
|
||||||
|
};
|
||||||
29
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.h
Normal file
29
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.h
Normal file
|
|
@ -0,0 +1,29 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __UVD_V3_1_H__
|
||||||
|
#define __UVD_V3_1_H__
|
||||||
|
|
||||||
|
extern const struct amdgpu_ip_block_version uvd_v3_1_ip_block;
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in a new issue