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spi: spi-qcom-qspi: Add DMA mode support
Current driver supports only PIO mode. HW supports DMA, so add DMA mode support to the driver for better performance for larger xfers. Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com Reviewed-by: Douglas Anderson <dianders@chromium.org Link: https://lore.kernel.org/r/1682328761-17517-6-git-send-email-quic_vnivarth@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org
This commit is contained in:
Vijaya Krishna Nivarthi
Mark Brown
parent
64c05eb3a0
commit
b5762d9560
1 changed files with 212 additions and 6 deletions
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@ -2,6 +2,8 @@
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// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
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#include <linux/clk.h>
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#include <linux/dmapool.h>
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#include <linux/dma-mapping.h>
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#include <linux/interconnect.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -62,6 +64,7 @@
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#define WR_FIFO_FULL BIT(10)
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#define WR_FIFO_OVERRUN BIT(11)
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#define TRANSACTION_DONE BIT(16)
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#define DMA_CHAIN_DONE BIT(31)
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#define QSPI_ERR_IRQS (RESP_FIFO_UNDERRUN | HRESP_FROM_NOC_ERR | \
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WR_FIFO_OVERRUN)
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#define QSPI_ALL_IRQS (QSPI_ERR_IRQS | RESP_FIFO_RDY | \
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@ -108,18 +111,34 @@
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#define RD_FIFO_RESET 0x0030
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#define RESET_FIFO BIT(0)
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#define NEXT_DMA_DESC_ADDR 0x0040
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#define CURRENT_DMA_DESC_ADDR 0x0044
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#define CURRENT_MEM_ADDR 0x0048
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#define CUR_MEM_ADDR 0x0048
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#define HW_VERSION 0x004c
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#define RD_FIFO 0x0050
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#define SAMPLING_CLK_CFG 0x0090
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#define SAMPLING_CLK_STATUS 0x0094
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#define QSPI_ALIGN_REQ 32
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enum qspi_dir {
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QSPI_READ,
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QSPI_WRITE,
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};
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struct qspi_cmd_desc {
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u32 data_address;
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u32 next_descriptor;
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u32 direction:1;
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u32 multi_io_mode:3;
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u32 reserved1:4;
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u32 fragment:1;
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u32 reserved2:7;
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u32 length:16;
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};
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struct qspi_xfer {
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union {
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const void *tx_buf;
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@ -137,11 +156,23 @@ enum qspi_clocks {
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QSPI_NUM_CLKS
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};
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/*
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* Number of entries in sgt returned from spi framework that-
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* will be supported. Can be modified as required.
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* In practice, given max_dma_len is 64KB, the number of
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* entries is not expected to exceed 1.
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*/
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#define QSPI_MAX_SG 5
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struct qcom_qspi {
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void __iomem *base;
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struct device *dev;
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struct clk_bulk_data *clks;
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struct qspi_xfer xfer;
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struct dma_pool *dma_cmd_pool;
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dma_addr_t dma_cmd_desc[QSPI_MAX_SG];
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void *virt_cmd_desc[QSPI_MAX_SG];
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unsigned int n_cmd_desc;
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struct icc_path *icc_path_cpu_to_qspi;
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unsigned long last_speed;
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/* Lock to protect data accessed by IRQs */
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@ -153,21 +184,22 @@ static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl,
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{
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switch (buswidth) {
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case 1:
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return SDR_1BIT << MULTI_IO_MODE_SHFT;
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return SDR_1BIT;
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case 2:
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return SDR_2BIT << MULTI_IO_MODE_SHFT;
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return SDR_2BIT;
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case 4:
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return SDR_4BIT << MULTI_IO_MODE_SHFT;
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return SDR_4BIT;
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default:
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dev_warn_once(ctrl->dev,
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"Unexpected bus width: %u\n", buswidth);
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return SDR_1BIT << MULTI_IO_MODE_SHFT;
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return SDR_1BIT;
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}
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}
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static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl)
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{
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u32 pio_xfer_cfg;
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u32 iomode;
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const struct qspi_xfer *xfer;
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xfer = &ctrl->xfer;
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@ -179,7 +211,8 @@ static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl)
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else
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pio_xfer_cfg |= TRANSFER_FRAGMENT;
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pio_xfer_cfg &= ~MULTI_IO_MODE_MSK;
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pio_xfer_cfg |= qspi_buswidth_to_iomode(ctrl, xfer->buswidth);
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iomode = qspi_buswidth_to_iomode(ctrl, xfer->buswidth);
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pio_xfer_cfg |= iomode << MULTI_IO_MODE_SHFT;
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writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG);
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}
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@ -217,12 +250,22 @@ static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl)
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static void qcom_qspi_handle_err(struct spi_master *master,
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struct spi_message *msg)
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{
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u32 int_status;
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struct qcom_qspi *ctrl = spi_master_get_devdata(master);
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unsigned long flags;
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int i;
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spin_lock_irqsave(&ctrl->lock, flags);
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writel(0, ctrl->base + MSTR_INT_EN);
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int_status = readl(ctrl->base + MSTR_INT_STATUS);
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writel(int_status, ctrl->base + MSTR_INT_STATUS);
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ctrl->xfer.rem_bytes = 0;
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/* free cmd descriptors if they are around (DMA mode) */
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for (i = 0; i < ctrl->n_cmd_desc; i++)
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dma_pool_free(ctrl->dma_cmd_pool, ctrl->virt_cmd_desc[i],
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ctrl->dma_cmd_desc[i]);
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ctrl->n_cmd_desc = 0;
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spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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@ -242,7 +285,7 @@ static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz)
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}
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/*
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* Set BW quota for CPU as driver supports FIFO mode only.
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* Set BW quota for CPU.
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* We don't have explicit peak requirement so keep it equal to avg_bw.
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*/
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avg_bw_cpu = Bps_to_icc(speed_hz);
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@ -258,6 +301,102 @@ static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz)
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return 0;
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}
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static int qcom_qspi_alloc_desc(struct qcom_qspi *ctrl, dma_addr_t dma_ptr,
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uint32_t n_bytes)
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{
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struct qspi_cmd_desc *virt_cmd_desc, *prev;
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dma_addr_t dma_cmd_desc;
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/* allocate for dma cmd descriptor */
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virt_cmd_desc = dma_pool_alloc(ctrl->dma_cmd_pool, GFP_KERNEL | __GFP_ZERO, &dma_cmd_desc);
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if (!virt_cmd_desc)
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return -ENOMEM;
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ctrl->virt_cmd_desc[ctrl->n_cmd_desc] = virt_cmd_desc;
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ctrl->dma_cmd_desc[ctrl->n_cmd_desc] = dma_cmd_desc;
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ctrl->n_cmd_desc++;
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/* setup cmd descriptor */
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virt_cmd_desc->data_address = dma_ptr;
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virt_cmd_desc->direction = ctrl->xfer.dir;
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virt_cmd_desc->multi_io_mode = qspi_buswidth_to_iomode(ctrl, ctrl->xfer.buswidth);
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virt_cmd_desc->fragment = !ctrl->xfer.is_last;
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virt_cmd_desc->length = n_bytes;
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/* update previous descriptor */
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if (ctrl->n_cmd_desc >= 2) {
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prev = (ctrl->virt_cmd_desc)[ctrl->n_cmd_desc - 2];
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prev->next_descriptor = dma_cmd_desc;
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prev->fragment = 1;
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}
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return 0;
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}
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static int qcom_qspi_setup_dma_desc(struct qcom_qspi *ctrl,
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struct spi_transfer *xfer)
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{
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int ret;
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struct sg_table *sgt;
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dma_addr_t dma_ptr_sg;
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unsigned int dma_len_sg;
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int i;
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if (ctrl->n_cmd_desc) {
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dev_err(ctrl->dev, "Remnant dma buffers n_cmd_desc-%d\n", ctrl->n_cmd_desc);
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return -EIO;
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}
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sgt = (ctrl->xfer.dir == QSPI_READ) ? &xfer->rx_sg : &xfer->tx_sg;
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if (!sgt->nents || sgt->nents > QSPI_MAX_SG) {
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dev_warn_once(ctrl->dev, "Cannot handle %d entries in scatter list\n", sgt->nents);
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return -EAGAIN;
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}
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for (i = 0; i < sgt->nents; i++) {
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dma_ptr_sg = sg_dma_address(sgt->sgl + i);
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if (!IS_ALIGNED(dma_ptr_sg, QSPI_ALIGN_REQ)) {
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dev_warn_once(ctrl->dev, "dma_address not aligned to %d\n", QSPI_ALIGN_REQ);
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return -EAGAIN;
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}
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}
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for (i = 0; i < sgt->nents; i++) {
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dma_ptr_sg = sg_dma_address(sgt->sgl + i);
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dma_len_sg = sg_dma_len(sgt->sgl + i);
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ret = qcom_qspi_alloc_desc(ctrl, dma_ptr_sg, dma_len_sg);
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if (ret)
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goto cleanup;
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}
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return 0;
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cleanup:
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for (i = 0; i < ctrl->n_cmd_desc; i++)
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dma_pool_free(ctrl->dma_cmd_pool, ctrl->virt_cmd_desc[i],
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ctrl->dma_cmd_desc[i]);
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ctrl->n_cmd_desc = 0;
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return ret;
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}
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static void qcom_qspi_dma_xfer(struct qcom_qspi *ctrl)
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{
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/* Setup new interrupts */
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writel(DMA_CHAIN_DONE, ctrl->base + MSTR_INT_EN);
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/* kick off transfer */
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writel((u32)((ctrl->dma_cmd_desc)[0]), ctrl->base + NEXT_DMA_DESC_ADDR);
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}
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/* Switch to DMA if transfer length exceeds this */
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#define QSPI_MAX_BYTES_FIFO 64
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static bool qcom_qspi_can_dma(struct spi_controller *ctlr,
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struct spi_device *slv, struct spi_transfer *xfer)
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{
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return xfer->len > QSPI_MAX_BYTES_FIFO;
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}
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static int qcom_qspi_transfer_one(struct spi_master *master,
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struct spi_device *slv,
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struct spi_transfer *xfer)
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@ -266,6 +405,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
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int ret;
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unsigned long speed_hz;
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unsigned long flags;
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u32 mstr_cfg;
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speed_hz = slv->max_speed_hz;
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if (xfer->speed_hz)
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@ -276,6 +416,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
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return ret;
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spin_lock_irqsave(&ctrl->lock, flags);
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mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
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/* We are half duplex, so either rx or tx will be set */
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if (xfer->rx_buf) {
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@ -290,10 +431,36 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
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ctrl->xfer.is_last = list_is_last(&xfer->transfer_list,
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&master->cur_msg->transfers);
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ctrl->xfer.rem_bytes = xfer->len;
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if (xfer->rx_sg.nents || xfer->tx_sg.nents) {
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/* do DMA transfer */
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if (!(mstr_cfg & DMA_ENABLE)) {
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mstr_cfg |= DMA_ENABLE;
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writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
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}
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ret = qcom_qspi_setup_dma_desc(ctrl, xfer);
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if (ret != -EAGAIN) {
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if (!ret)
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qcom_qspi_dma_xfer(ctrl);
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goto exit;
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}
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dev_warn_once(ctrl->dev, "DMA failure, falling back to PIO");
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ret = 0; /* We'll retry w/ PIO */
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}
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if (mstr_cfg & DMA_ENABLE) {
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mstr_cfg &= ~DMA_ENABLE;
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writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
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}
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qcom_qspi_pio_xfer(ctrl);
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exit:
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spin_unlock_irqrestore(&ctrl->lock, flags);
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if (ret)
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return ret;
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/* We'll call spi_finalize_current_transfer() when done */
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return 1;
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}
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@ -328,6 +495,16 @@ static int qcom_qspi_prepare_message(struct spi_master *master,
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return 0;
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}
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static int qcom_qspi_alloc_dma(struct qcom_qspi *ctrl)
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{
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ctrl->dma_cmd_pool = dmam_pool_create("qspi cmd desc pool",
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ctrl->dev, sizeof(struct qspi_cmd_desc), 0, 0);
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if (!ctrl->dma_cmd_pool)
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return -ENOMEM;
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return 0;
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}
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static irqreturn_t pio_read(struct qcom_qspi *ctrl)
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{
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u32 rd_fifo_status;
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@ -426,6 +603,7 @@ static irqreturn_t qcom_qspi_irq(int irq, void *dev_id)
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int_status = readl(ctrl->base + MSTR_INT_STATUS);
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writel(int_status, ctrl->base + MSTR_INT_STATUS);
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/* PIO mode handling */
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if (ctrl->xfer.dir == QSPI_WRITE) {
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if (int_status & WR_FIFO_EMPTY)
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ret = pio_write(ctrl);
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@ -449,6 +627,22 @@ static irqreturn_t qcom_qspi_irq(int irq, void *dev_id)
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spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
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}
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/* DMA mode handling */
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if (int_status & DMA_CHAIN_DONE) {
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int i;
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writel(0, ctrl->base + MSTR_INT_EN);
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ctrl->xfer.rem_bytes = 0;
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for (i = 0; i < ctrl->n_cmd_desc; i++)
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dma_pool_free(ctrl->dma_cmd_pool, ctrl->virt_cmd_desc[i],
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ctrl->dma_cmd_desc[i]);
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ctrl->n_cmd_desc = 0;
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ret = IRQ_HANDLED;
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spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
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}
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spin_unlock(&ctrl->lock);
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return ret;
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}
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@ -517,7 +711,13 @@ static int qcom_qspi_probe(struct platform_device *pdev)
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return ret;
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}
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (ret)
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return dev_err_probe(dev, ret, "could not set DMA mask\n");
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master->max_speed_hz = 300000000;
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master->max_dma_len = 65536; /* as per HPG */
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master->dma_alignment = QSPI_ALIGN_REQ;
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master->num_chipselect = QSPI_NUM_CS;
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master->bus_num = -1;
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master->dev.of_node = pdev->dev.of_node;
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@ -528,6 +728,8 @@ static int qcom_qspi_probe(struct platform_device *pdev)
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master->prepare_message = qcom_qspi_prepare_message;
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master->transfer_one = qcom_qspi_transfer_one;
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master->handle_err = qcom_qspi_handle_err;
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if (of_property_read_bool(pdev->dev.of_node, "iommus"))
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master->can_dma = qcom_qspi_can_dma;
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master->auto_runtime_pm = true;
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ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
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@ -540,6 +742,10 @@ static int qcom_qspi_probe(struct platform_device *pdev)
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return ret;
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}
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ret = qcom_qspi_alloc_dma(ctrl);
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if (ret)
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return ret;
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_autosuspend_delay(dev, 250);
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pm_runtime_enable(dev);
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