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clk: socfpga: Look for the GPIO_DB_CLK by its offset

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After the patch:
"clk: socfpga: Map the clk manager base address in the clock driver"

The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace
looking for the GPIO_DB_CLK by its divider offset instead.

Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as
this represents the GPIO_DB_CLK.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
This commit is contained in:
Dinh Nguyen 2013-12-13 16:38:28 -06:00 committed by Mike Turquette
parent 6a7e71221d
commit b7cec13f08
1 changed files with 3 additions and 2 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/clk/socfpga/clk.c
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@ -51,7 +51,7 @@
#define SOCFPGA_NAND_CLK "nand_clk" #define SOCFPGA_NAND_CLK "nand_clk"
#define SOCFPGA_NAND_X_CLK "nand_x_clk" #define SOCFPGA_NAND_X_CLK "nand_x_clk"
#define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_MMC_CLK "sdmmc_clk"
#define SOCFPGA_DB_CLK "gpio_db_clk" #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
#define div_mask(width) ((1 << (width)) - 1) #define div_mask(width) ((1 << (width)) - 1)
#define streq(a, b) (strcmp((a), (b)) == 0) #define streq(a, b) (strcmp((a), (b)) == 0)
@ -234,7 +234,8 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
else if (socfpgaclk->div_reg) { else if (socfpgaclk->div_reg) {
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
val &= div_mask(socfpgaclk->width); val &= div_mask(socfpgaclk->width);
if (streq(hwclk->init->name, SOCFPGA_DB_CLK)) /* Check for GPIO_DB_CLK by its offset */
if ((int)socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
div = val + 1; div = val + 1;
else else
div = (1 << val); div = (1 << val);