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i2c: jz4780: Add i2c bus controller driver for Ingenic JZ4780
Adds the i2c bus controller driver for the Ingenic JZ4780 SoC. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Zubair Lutfullah Kakakhel
Wolfram Sang
parent
3b10db23c0
commit
ba92222ed6
4 changed files with 877 additions and 0 deletions
35
Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
Normal file
35
Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
Normal file
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@ -0,0 +1,35 @@
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* Ingenic JZ4780 I2C Bus controller
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Required properties:
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- compatible: should be "ingenic,jz4780-i2c"
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- reg: Should contain the address & size of the I2C controller registers.
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- interrupts: Should specify the interrupt provided by parent.
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- clocks: Should contain a single clock specifier for the JZ4780 I2C clock.
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- clock-frequency: desired I2C bus clock frequency in Hz.
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Recommended properties:
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- pinctrl-names: should be "default";
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- pinctrl-0: phandle to pinctrl function
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Optional properties:
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- interrupt-parent: Should be the phandle of the interrupt controller that
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delivers interrupts to the I2C block.
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Example
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/ {
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i2c4: i2c4@0x10054000 {
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compatible = "ingenic,jz4780-i2c";
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reg = <0x10054000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <56>;
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clocks = <&cgu JZ4780_CLK_SMB4>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pins_i2c4_data>;
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};
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};
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@ -583,6 +583,15 @@ config I2C_IOP3XX
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This driver can also be built as a module. If so, the module
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will be called i2c-iop3xx.
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config I2C_JZ4780
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tristate "JZ4780 I2C controller interface support"
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depends on MACH_JZ4780 || COMPILE_TEST
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help
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If you say yes to this option, support will be included for the
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Ingenic JZ4780 I2C controller.
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If you don't know what to do here, say N.
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config I2C_KEMPLD
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tristate "Kontron COM I2C Controller"
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depends on MFD_KEMPLD
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@ -56,6 +56,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
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obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o
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obj-$(CONFIG_I2C_IMX) += i2c-imx.o
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obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
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obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
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obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
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obj-$(CONFIG_I2C_MESON) += i2c-meson.o
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obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
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832
drivers/i2c/busses/i2c-jz4780.c
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832
drivers/i2c/busses/i2c-jz4780.c
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@ -0,0 +1,832 @@
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/*
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* Ingenic JZ4780 I2C bus driver
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*
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* Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
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* Copyright (C) 2015 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#define JZ4780_I2C_CTRL 0x00
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#define JZ4780_I2C_TAR 0x04
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#define JZ4780_I2C_SAR 0x08
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#define JZ4780_I2C_DC 0x10
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#define JZ4780_I2C_SHCNT 0x14
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#define JZ4780_I2C_SLCNT 0x18
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#define JZ4780_I2C_FHCNT 0x1C
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#define JZ4780_I2C_FLCNT 0x20
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#define JZ4780_I2C_INTST 0x2C
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#define JZ4780_I2C_INTM 0x30
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#define JZ4780_I2C_RXTL 0x38
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#define JZ4780_I2C_TXTL 0x3C
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#define JZ4780_I2C_CINTR 0x40
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#define JZ4780_I2C_CRXUF 0x44
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#define JZ4780_I2C_CRXOF 0x48
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#define JZ4780_I2C_CTXOF 0x4C
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#define JZ4780_I2C_CRXREQ 0x50
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#define JZ4780_I2C_CTXABRT 0x54
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#define JZ4780_I2C_CRXDONE 0x58
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#define JZ4780_I2C_CACT 0x5C
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#define JZ4780_I2C_CSTP 0x60
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#define JZ4780_I2C_CSTT 0x64
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#define JZ4780_I2C_CGC 0x68
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#define JZ4780_I2C_ENB 0x6C
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#define JZ4780_I2C_STA 0x70
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#define JZ4780_I2C_TXABRT 0x80
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#define JZ4780_I2C_DMACR 0x88
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#define JZ4780_I2C_DMATDLR 0x8C
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#define JZ4780_I2C_DMARDLR 0x90
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#define JZ4780_I2C_SDASU 0x94
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#define JZ4780_I2C_ACKGC 0x98
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#define JZ4780_I2C_ENSTA 0x9C
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#define JZ4780_I2C_SDAHD 0xD0
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#define JZ4780_I2C_CTRL_STPHLD BIT(7)
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#define JZ4780_I2C_CTRL_SLVDIS BIT(6)
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#define JZ4780_I2C_CTRL_REST BIT(5)
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#define JZ4780_I2C_CTRL_MATP BIT(4)
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#define JZ4780_I2C_CTRL_SATP BIT(3)
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#define JZ4780_I2C_CTRL_SPDF BIT(2)
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#define JZ4780_I2C_CTRL_SPDS BIT(1)
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#define JZ4780_I2C_CTRL_MD BIT(0)
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#define JZ4780_I2C_STA_SLVACT BIT(6)
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#define JZ4780_I2C_STA_MSTACT BIT(5)
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#define JZ4780_I2C_STA_RFF BIT(4)
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#define JZ4780_I2C_STA_RFNE BIT(3)
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#define JZ4780_I2C_STA_TFE BIT(2)
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#define JZ4780_I2C_STA_TFNF BIT(1)
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#define JZ4780_I2C_STA_ACT BIT(0)
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static const char * const jz4780_i2c_abrt_src[] = {
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"ABRT_7B_ADDR_NOACK",
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"ABRT_10ADDR1_NOACK",
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"ABRT_10ADDR2_NOACK",
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"ABRT_XDATA_NOACK",
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"ABRT_GCALL_NOACK",
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"ABRT_GCALL_READ",
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"ABRT_HS_ACKD",
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"SBYTE_ACKDET",
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"ABRT_HS_NORSTRT",
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"SBYTE_NORSTRT",
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"ABRT_10B_RD_NORSTRT",
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"ABRT_MASTER_DIS",
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"ARB_LOST",
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"SLVFLUSH_TXFIFO",
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"SLV_ARBLOST",
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"SLVRD_INTX",
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};
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#define JZ4780_I2C_INTST_IGC BIT(11)
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#define JZ4780_I2C_INTST_ISTT BIT(10)
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#define JZ4780_I2C_INTST_ISTP BIT(9)
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#define JZ4780_I2C_INTST_IACT BIT(8)
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#define JZ4780_I2C_INTST_RXDN BIT(7)
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#define JZ4780_I2C_INTST_TXABT BIT(6)
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#define JZ4780_I2C_INTST_RDREQ BIT(5)
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#define JZ4780_I2C_INTST_TXEMP BIT(4)
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#define JZ4780_I2C_INTST_TXOF BIT(3)
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#define JZ4780_I2C_INTST_RXFL BIT(2)
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#define JZ4780_I2C_INTST_RXOF BIT(1)
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#define JZ4780_I2C_INTST_RXUF BIT(0)
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#define JZ4780_I2C_INTM_MIGC BIT(11)
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#define JZ4780_I2C_INTM_MISTT BIT(10)
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#define JZ4780_I2C_INTM_MISTP BIT(9)
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#define JZ4780_I2C_INTM_MIACT BIT(8)
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#define JZ4780_I2C_INTM_MRXDN BIT(7)
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#define JZ4780_I2C_INTM_MTXABT BIT(6)
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#define JZ4780_I2C_INTM_MRDREQ BIT(5)
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#define JZ4780_I2C_INTM_MTXEMP BIT(4)
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#define JZ4780_I2C_INTM_MTXOF BIT(3)
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#define JZ4780_I2C_INTM_MRXFL BIT(2)
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#define JZ4780_I2C_INTM_MRXOF BIT(1)
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#define JZ4780_I2C_INTM_MRXUF BIT(0)
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#define JZ4780_I2C_DC_READ BIT(8)
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#define JZ4780_I2C_SDAHD_HDENB BIT(8)
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#define JZ4780_I2C_ENB_I2C BIT(0)
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#define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
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#define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
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#define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
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#define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
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#define JZ4780_I2C_FIFO_LEN 16
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#define TX_LEVEL 3
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#define RX_LEVEL (JZ4780_I2C_FIFO_LEN - TX_LEVEL - 1)
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#define JZ4780_I2C_TIMEOUT 300
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#define BUFSIZE 200
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struct jz4780_i2c {
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void __iomem *iomem;
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int irq;
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struct clk *clk;
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struct i2c_adapter adap;
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/* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */
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spinlock_t lock;
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/* beginning of lock scope */
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unsigned char *rbuf;
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int rd_total_len;
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int rd_data_xfered;
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int rd_cmd_xfered;
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unsigned char *wbuf;
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int wt_len;
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int is_write;
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int stop_hold;
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int speed;
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int data_buf[BUFSIZE];
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int cmd_buf[BUFSIZE];
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int cmd;
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/* end of lock scope */
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struct completion trans_waitq;
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};
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static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
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unsigned long offset)
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{
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return readw(i2c->iomem + offset);
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}
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static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
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unsigned long offset, unsigned short val)
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{
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writew(val, i2c->iomem + offset);
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}
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static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
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{
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unsigned short regval;
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unsigned long loops = 5;
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jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
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do {
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regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
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if (!(regval & JZ4780_I2C_ENB_I2C))
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return 0;
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usleep_range(5000, 15000);
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} while (--loops);
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dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
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return -ETIMEDOUT;
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}
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static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
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{
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unsigned short regval;
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unsigned long loops = 5;
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jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
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do {
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regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
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if (regval & JZ4780_I2C_ENB_I2C)
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return 0;
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usleep_range(5000, 15000);
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} while (--loops);
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dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
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return -ETIMEDOUT;
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}
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static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
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{
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unsigned short regval;
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unsigned long loops = 5;
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do {
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regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
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if ((regval & JZ4780_I2C_STA_TFE) &&
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!(regval & JZ4780_I2C_STA_MSTACT))
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break;
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usleep_range(5000, 15000);
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} while (--loops);
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if (loops) {
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jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
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return 0;
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}
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dev_err(&i2c->adap.dev,
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"set device to address 0x%02x failed, STA=0x%04x\n",
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address, regval);
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return -ENXIO;
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}
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static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
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{
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int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
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int cnt_high = 0; /* HIGH period count of the SCL clock */
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int cnt_low = 0; /* LOW period count of the SCL clock */
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int cnt_period = 0; /* period count of the SCL clock */
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int setup_time = 0;
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int hold_time = 0;
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unsigned short tmp = 0;
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int i2c_clk = i2c->speed;
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if (jz4780_i2c_disable(i2c))
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dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
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/*
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* 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
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* standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
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* fast mode, min LOW and HIGH period are 1300 ns and 600 ns
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*/
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cnt_period = dev_clk_khz / i2c_clk;
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if (i2c_clk <= 100)
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cnt_high = (cnt_period * 4000) / (4700 + 4000);
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else
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cnt_high = (cnt_period * 600) / (1300 + 600);
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cnt_low = cnt_period - cnt_high;
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/*
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* NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because
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* normal read are 2 messages, we cannot disable i2c controller
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* between these two messages, this means that we must always set
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* JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL
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*
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*/
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if (i2c_clk <= 100) {
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tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
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| JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
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jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
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jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
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JZ4780_I2CSHCNT_ADJUST(cnt_high));
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jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
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JZ4780_I2CSLCNT_ADJUST(cnt_low));
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} else {
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tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
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| JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
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jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
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jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
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JZ4780_I2CFHCNT_ADJUST(cnt_high));
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jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
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JZ4780_I2CFLCNT_ADJUST(cnt_low));
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}
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/*
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* a i2c device must internally provide a hold time at least 300ns
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* tHD:DAT
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* Standard Mode: min=300ns, max=3450ns
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* Fast Mode: min=0ns, max=900ns
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* tSU:DAT
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* Standard Mode: min=250ns, max=infinite
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* Fast Mode: min=100(250ns is recommended), max=infinite
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*
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* 1i2c_clk = 10^6 / dev_clk_khz
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* on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
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* on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
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*
|
||||
* The actual hold time is (SDAHD + 1) * (i2c_clk period).
|
||||
*
|
||||
* Length of setup time calculated using (SDASU - 1) * (ic_clk_period)
|
||||
*
|
||||
*/
|
||||
if (i2c_clk <= 100) { /* standard mode */
|
||||
setup_time = 300;
|
||||
hold_time = 400;
|
||||
} else {
|
||||
setup_time = 450;
|
||||
hold_time = 450;
|
||||
}
|
||||
|
||||
hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
|
||||
setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
|
||||
|
||||
if (setup_time > 255)
|
||||
setup_time = 255;
|
||||
|
||||
if (setup_time <= 0)
|
||||
setup_time = 1;
|
||||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
|
||||
|
||||
if (hold_time > 255)
|
||||
hold_time = 255;
|
||||
|
||||
if (hold_time >= 0) {
|
||||
/*i2c hold time enable */
|
||||
hold_time |= JZ4780_I2C_SDAHD_HDENB;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
|
||||
} else {
|
||||
/* disable hold time */
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
|
||||
{
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
unsigned short tmp;
|
||||
|
||||
spin_lock_irqsave(&i2c->lock, flags);
|
||||
|
||||
/* can send stop now if need */
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
|
||||
tmp &= ~JZ4780_I2C_CTRL_STPHLD;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
|
||||
/* disable all interrupts first */
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
|
||||
|
||||
/* then clear all interrupts */
|
||||
jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
|
||||
jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
|
||||
|
||||
/* then disable the controller */
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
|
||||
tmp &= ~JZ4780_I2C_ENB_I2C;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
udelay(10);
|
||||
tmp |= JZ4780_I2C_ENB_I2C;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
|
||||
spin_unlock_irqrestore(&i2c->lock, flags);
|
||||
|
||||
ret = jz4780_i2c_disable(i2c);
|
||||
if (ret)
|
||||
dev_err(&i2c->adap.dev,
|
||||
"unable to disable device during cleanup!\n");
|
||||
|
||||
if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
|
||||
& jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
|
||||
dev_err(&i2c->adap.dev,
|
||||
"device has interrupts after a complete cleanup!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
|
||||
{
|
||||
jz4780_i2c_set_speed(i2c);
|
||||
return jz4780_i2c_enable(i2c);
|
||||
}
|
||||
|
||||
static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, int cmd_count)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < cmd_count; i++)
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
|
||||
}
|
||||
|
||||
static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
|
||||
{
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
|
||||
complete(&i2c->trans_waitq);
|
||||
}
|
||||
|
||||
static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
|
||||
{
|
||||
unsigned short tmp;
|
||||
unsigned short intst;
|
||||
unsigned short intmsk;
|
||||
struct jz4780_i2c *i2c = dev_id;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i2c->lock, flags);
|
||||
intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
|
||||
intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
|
||||
|
||||
intst &= intmsk;
|
||||
|
||||
if (intst & JZ4780_I2C_INTST_TXABT) {
|
||||
jz4780_i2c_trans_done(i2c);
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (intst & JZ4780_I2C_INTST_RXOF) {
|
||||
dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
|
||||
jz4780_i2c_trans_done(i2c);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* When reading, always drain RX FIFO before we send more Read
|
||||
* Commands to avoid fifo overrun
|
||||
*/
|
||||
if (i2c->is_write == 0) {
|
||||
int rd_left;
|
||||
|
||||
while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
|
||||
& JZ4780_I2C_STA_RFNE)) {
|
||||
*(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
|
||||
& 0xff;
|
||||
i2c->rd_data_xfered++;
|
||||
if (i2c->rd_data_xfered == i2c->rd_total_len) {
|
||||
jz4780_i2c_trans_done(i2c);
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
|
||||
|
||||
if (rd_left <= JZ4780_I2C_FIFO_LEN)
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
|
||||
}
|
||||
|
||||
if (intst & JZ4780_I2C_INTST_TXEMP) {
|
||||
if (i2c->is_write == 0) {
|
||||
int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
|
||||
int max_send = (JZ4780_I2C_FIFO_LEN - 1)
|
||||
- (i2c->rd_cmd_xfered
|
||||
- i2c->rd_data_xfered);
|
||||
int cmd_to_send = min(cmd_left, max_send);
|
||||
|
||||
if (i2c->rd_cmd_xfered != 0)
|
||||
cmd_to_send = min(cmd_to_send,
|
||||
JZ4780_I2C_FIFO_LEN
|
||||
- TX_LEVEL - 1);
|
||||
|
||||
if (cmd_to_send) {
|
||||
jz4780_i2c_send_rcmd(i2c, cmd_to_send);
|
||||
i2c->rd_cmd_xfered += cmd_to_send;
|
||||
}
|
||||
|
||||
cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
|
||||
if (cmd_left == 0) {
|
||||
intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
|
||||
intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
|
||||
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
|
||||
tmp &= ~JZ4780_I2C_CTRL_STPHLD;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
}
|
||||
} else {
|
||||
unsigned short data;
|
||||
unsigned short i2c_sta;
|
||||
|
||||
i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
|
||||
|
||||
while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
|
||||
(i2c->wt_len > 0)) {
|
||||
i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
|
||||
data = *i2c->wbuf;
|
||||
data &= ~JZ4780_I2C_DC_READ;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
|
||||
data);
|
||||
i2c->wbuf++;
|
||||
i2c->wt_len--;
|
||||
}
|
||||
|
||||
if (i2c->wt_len == 0) {
|
||||
if (!i2c->stop_hold) {
|
||||
tmp = jz4780_i2c_readw(i2c,
|
||||
JZ4780_I2C_CTRL);
|
||||
tmp &= ~JZ4780_I2C_CTRL_STPHLD;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL,
|
||||
tmp);
|
||||
}
|
||||
|
||||
jz4780_i2c_trans_done(i2c);
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
done:
|
||||
spin_unlock_irqrestore(&i2c->lock, flags);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
|
||||
{
|
||||
int i;
|
||||
|
||||
dev_err(&i2c->adap.dev, "txabrt: 0x%08x\n", src);
|
||||
dev_err(&i2c->adap.dev, "device addr=%x\n",
|
||||
jz4780_i2c_readw(i2c, JZ4780_I2C_TAR));
|
||||
dev_err(&i2c->adap.dev, "send cmd count:%d %d\n",
|
||||
i2c->cmd, i2c->cmd_buf[i2c->cmd]);
|
||||
dev_err(&i2c->adap.dev, "receive data count:%d %d\n",
|
||||
i2c->cmd, i2c->data_buf[i2c->cmd]);
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (src & BIT(i))
|
||||
dev_dbg(&i2c->adap.dev, "I2C TXABRT[%d]=%s\n",
|
||||
i, jz4780_i2c_abrt_src[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
|
||||
unsigned char *buf, int len, int cnt,
|
||||
int idx)
|
||||
{
|
||||
int ret = 0;
|
||||
long timeout;
|
||||
int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
|
||||
unsigned short tmp;
|
||||
unsigned long flags;
|
||||
|
||||
memset(buf, 0, len);
|
||||
|
||||
spin_lock_irqsave(&i2c->lock, flags);
|
||||
|
||||
i2c->stop_hold = 0;
|
||||
i2c->is_write = 0;
|
||||
i2c->rbuf = buf;
|
||||
i2c->rd_total_len = len;
|
||||
i2c->rd_data_xfered = 0;
|
||||
i2c->rd_cmd_xfered = 0;
|
||||
|
||||
if (len <= JZ4780_I2C_FIFO_LEN)
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
|
||||
else
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, RX_LEVEL);
|
||||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
|
||||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
|
||||
JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
|
||||
| JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
|
||||
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
|
||||
tmp |= JZ4780_I2C_CTRL_STPHLD;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
|
||||
spin_unlock_irqrestore(&i2c->lock, flags);
|
||||
|
||||
timeout = wait_for_completion_timeout(&i2c->trans_waitq,
|
||||
msecs_to_jiffies(wait_time));
|
||||
|
||||
if (!timeout) {
|
||||
dev_err(&i2c->adap.dev, "irq read timeout\n");
|
||||
dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
|
||||
i2c->cmd, i2c->cmd_buf[i2c->cmd]);
|
||||
dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
|
||||
i2c->cmd, i2c->data_buf[i2c->cmd]);
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
|
||||
if (tmp) {
|
||||
jz4780_i2c_txabrt(i2c, tmp);
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
|
||||
unsigned char *buf, int len,
|
||||
int cnt, int idx)
|
||||
{
|
||||
int ret = 0;
|
||||
int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
|
||||
long timeout;
|
||||
unsigned short tmp;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i2c->lock, flags);
|
||||
|
||||
if (idx < (cnt - 1))
|
||||
i2c->stop_hold = 1;
|
||||
else
|
||||
i2c->stop_hold = 0;
|
||||
|
||||
i2c->is_write = 1;
|
||||
i2c->wbuf = buf;
|
||||
i2c->wt_len = len;
|
||||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
|
||||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
|
||||
| JZ4780_I2C_INTM_MTXABT);
|
||||
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
|
||||
tmp |= JZ4780_I2C_CTRL_STPHLD;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
|
||||
spin_unlock_irqrestore(&i2c->lock, flags);
|
||||
|
||||
timeout = wait_for_completion_timeout(&i2c->trans_waitq,
|
||||
msecs_to_jiffies(wait_time));
|
||||
if (timeout && !i2c->stop_hold) {
|
||||
unsigned short i2c_sta;
|
||||
int write_in_process;
|
||||
|
||||
timeout = JZ4780_I2C_TIMEOUT * 100;
|
||||
for (; timeout > 0; timeout--) {
|
||||
i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
|
||||
|
||||
write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
|
||||
!(i2c_sta & JZ4780_I2C_STA_TFE);
|
||||
if (!write_in_process)
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
dev_err(&i2c->adap.dev, "write wait timeout\n");
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
|
||||
if (tmp) {
|
||||
jz4780_i2c_txabrt(i2c, tmp);
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
|
||||
int count)
|
||||
{
|
||||
int i = -EIO;
|
||||
int ret = 0;
|
||||
struct jz4780_i2c *i2c = adap->algo_data;
|
||||
|
||||
ret = jz4780_i2c_prepare(i2c);
|
||||
if (ret) {
|
||||
dev_err(&i2c->adap.dev, "I2C prepare failed\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
|
||||
ret = jz4780_i2c_set_target(i2c, msg->addr);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
for (i = 0; i < count; i++, msg++) {
|
||||
if (msg->flags & I2C_M_RD)
|
||||
ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
|
||||
count, i);
|
||||
else
|
||||
ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
|
||||
count, i);
|
||||
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = i;
|
||||
|
||||
out:
|
||||
jz4780_i2c_cleanup(i2c);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm jz4780_i2c_algorithm = {
|
||||
.master_xfer = jz4780_i2c_xfer,
|
||||
.functionality = jz4780_i2c_functionality,
|
||||
};
|
||||
|
||||
static const struct of_device_id jz4780_i2c_of_matches[] = {
|
||||
{ .compatible = "ingenic,jz4780-i2c", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int jz4780_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int clk_freq = 0;
|
||||
unsigned short tmp;
|
||||
struct resource *r;
|
||||
struct jz4780_i2c *i2c;
|
||||
|
||||
i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
|
||||
if (!i2c)
|
||||
return -ENOMEM;
|
||||
|
||||
i2c->adap.owner = THIS_MODULE;
|
||||
i2c->adap.algo = &jz4780_i2c_algorithm;
|
||||
i2c->adap.algo_data = i2c;
|
||||
i2c->adap.retries = 5;
|
||||
i2c->adap.dev.parent = &pdev->dev;
|
||||
i2c->adap.dev.of_node = pdev->dev.of_node;
|
||||
sprintf(i2c->adap.name, "%s", pdev->name);
|
||||
|
||||
init_completion(&i2c->trans_waitq);
|
||||
spin_lock_init(&i2c->lock);
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
i2c->iomem = devm_ioremap_resource(&pdev->dev, r);
|
||||
if (IS_ERR(i2c->iomem))
|
||||
return PTR_ERR(i2c->iomem);
|
||||
|
||||
platform_set_drvdata(pdev, i2c);
|
||||
|
||||
i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(i2c->clk))
|
||||
return PTR_ERR(i2c->clk);
|
||||
|
||||
clk_prepare_enable(i2c->clk);
|
||||
|
||||
if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
|
||||
&clk_freq)) {
|
||||
dev_err(&pdev->dev, "clock-frequency not specified in DT");
|
||||
return clk_freq;
|
||||
}
|
||||
|
||||
i2c->speed = clk_freq / 1000;
|
||||
jz4780_i2c_set_speed(i2c);
|
||||
|
||||
dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
|
||||
|
||||
tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
|
||||
tmp &= ~JZ4780_I2C_CTRL_STPHLD;
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
|
||||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
|
||||
|
||||
i2c->cmd = 0;
|
||||
memset(i2c->cmd_buf, 0, BUFSIZE);
|
||||
memset(i2c->data_buf, 0, BUFSIZE);
|
||||
|
||||
i2c->irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
|
||||
dev_name(&pdev->dev), i2c);
|
||||
if (ret) {
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = i2c_add_adapter(&i2c->adap);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to add bus\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
clk_disable_unprepare(i2c->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int jz4780_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(i2c->clk);
|
||||
i2c_del_adapter(&i2c->adap);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver jz4780_i2c_driver = {
|
||||
.probe = jz4780_i2c_probe,
|
||||
.remove = jz4780_i2c_remove,
|
||||
.driver = {
|
||||
.name = "jz4780-i2c",
|
||||
.of_match_table = of_match_ptr(jz4780_i2c_of_matches),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(jz4780_i2c_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
|
||||
MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");
|
||||
Loading…
Reference in a new issue