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ARM: mx27: Replace clk_register_clkdev with clock DT lookup
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance task for the clock devices easier. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Fabio Estevam
Shawn Guo
parent
52c9aa9461
commit
c20736f1ab
4 changed files with 158 additions and 17 deletions
117
Documentation/devicetree/bindings/clock/imx27-clock.txt
Normal file
117
Documentation/devicetree/bindings/clock/imx27-clock.txt
Normal file
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@ -0,0 +1,117 @@
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* Clock bindings for Freescale i.MX27
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Required properties:
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- compatible: Should be "fsl,imx27-ccm"
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX27
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clocks and IDs.
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Clock ID
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-----------------------
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dummy 0
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ckih 1
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ckil 2
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mpll 3
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spll 4
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mpll_main2 5
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ahb 6
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ipg 7
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nfc_div 8
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per1_div 9
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per2_div 10
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per3_div 11
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per4_div 12
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vpu_sel 13
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vpu_div 14
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usb_div 15
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cpu_sel 16
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clko_sel 17
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cpu_div 18
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clko_div 19
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ssi1_sel 20
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ssi2_sel 21
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ssi1_div 22
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ssi2_div 23
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clko_en 24
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ssi2_ipg_gate 25
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ssi1_ipg_gate 26
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slcdc_ipg_gate 27
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sdhc3_ipg_gate 28
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sdhc2_ipg_gate 29
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sdhc1_ipg_gate 30
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scc_ipg_gate 31
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sahara_ipg_gate 32
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rtc_ipg_gate 33
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pwm_ipg_gate 34
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owire_ipg_gate 35
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lcdc_ipg_gate 36
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kpp_ipg_gate 37
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iim_ipg_gate 38
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i2c2_ipg_gate 39
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i2c1_ipg_gate 40
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gpt6_ipg_gate 41
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gpt5_ipg_gate 42
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gpt4_ipg_gate 43
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gpt3_ipg_gate 44
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gpt2_ipg_gate 45
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gpt1_ipg_gate 46
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gpio_ipg_gate 47
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fec_ipg_gate 48
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emma_ipg_gate 49
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dma_ipg_gate 50
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cspi3_ipg_gate 51
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cspi2_ipg_gate 52
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cspi1_ipg_gate 53
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nfc_baud_gate 54
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ssi2_baud_gate 55
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ssi1_baud_gate 56
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vpu_baud_gate 57
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per4_gate 58
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per3_gate 59
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per2_gate 60
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per1_gate 61
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usb_ahb_gate 62
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slcdc_ahb_gate 63
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sahara_ahb_gate 64
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lcdc_ahb_gate 65
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vpu_ahb_gate 66
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fec_ahb_gate 67
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emma_ahb_gate 68
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emi_ahb_gate 69
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dma_ahb_gate 70
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csi_ahb_gate 71
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brom_ahb_gate 72
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ata_ahb_gate 73
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wdog_ipg_gate 74
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usb_ipg_gate 75
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uart6_ipg_gate 76
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uart5_ipg_gate 77
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uart4_ipg_gate 78
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uart3_ipg_gate 79
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uart2_ipg_gate 80
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uart1_ipg_gate 81
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ckih_div1p5 82
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fpm 83
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mpll_osc_sel 84
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mpll_sel 85
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Examples:
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks 81>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -62,12 +62,15 @@ wdog: wdog@10002000 {
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compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
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reg = <0x10002000 0x4000>;
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interrupts = <27>;
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clocks = <&clks 0>;
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks 81>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -75,6 +78,8 @@ uart2: serial@1000b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000b000 0x1000>;
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interrupts = <19>;
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clocks = <&clks 80>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -82,6 +87,8 @@ uart3: serial@1000c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000c000 0x1000>;
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interrupts = <18>;
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clocks = <&clks 79>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -89,6 +96,8 @@ uart4: serial@1000d000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000d000 0x1000>;
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interrupts = <17>;
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clocks = <&clks 78>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -98,6 +107,8 @@ cspi1: cspi@1000e000 {
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compatible = "fsl,imx27-cspi";
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reg = <0x1000e000 0x1000>;
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interrupts = <16>;
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clocks = <&clks 53>, <&clks 0>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -107,6 +118,8 @@ cspi2: cspi@1000f000 {
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compatible = "fsl,imx27-cspi";
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reg = <0x1000f000 0x1000>;
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interrupts = <15>;
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clocks = <&clks 52>, <&clks 0>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -116,6 +129,7 @@ i2c1: i2c@10012000 {
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x10012000 0x1000>;
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interrupts = <12>;
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clocks = <&clks 40>;
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status = "disabled";
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};
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@ -185,6 +199,8 @@ cspi3: cspi@10017000 {
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compatible = "fsl,imx27-cspi";
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reg = <0x10017000 0x1000>;
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interrupts = <6>;
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clocks = <&clks 51>, <&clks 0>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -192,6 +208,8 @@ uart5: serial@1001b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001b000 0x1000>;
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interrupts = <49>;
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clocks = <&clks 77>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -199,6 +217,8 @@ uart6: serial@1001c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001c000 0x1000>;
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interrupts = <48>;
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clocks = <&clks 78>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -208,6 +228,7 @@ i2c2: i2c@1001d000 {
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x1001d000 0x1000>;
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interrupts = <1>;
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clocks = <&clks 39>;
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status = "disabled";
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};
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@ -224,10 +245,19 @@ fec: ethernet@1002b000 {
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compatible = "fsl,imx27-fec";
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reg = <0x1002b000 0x4000>;
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interrupts = <50>;
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clocks = <&clks 48>, <&clks 67>, <&clks 0>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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};
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nfc: nand@d8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -235,6 +265,7 @@ nfc: nand@d8000000 {
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compatible = "fsl,imx27-nand";
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reg = <0xd8000000 0x1000>;
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interrupts = <29>;
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clocks = <&clks 54>;
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status = "disabled";
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};
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};
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@ -86,10 +86,12 @@ enum mx27_clks {
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};
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static struct clk *clk[clk_max];
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static struct clk_onecell_data clk_data;
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int __init mx27_clocks_init(unsigned long fref)
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{
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int i;
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struct device_node *np;
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckih] = imx_clk_fixed("ckih", fref);
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@ -198,6 +200,13 @@ int __init mx27_clocks_init(unsigned long fref)
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pr_err("i.MX27 clk %d: register failed with %ld\n",
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i, PTR_ERR(clk[i]));
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np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
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if (np) {
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
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clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
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clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
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@ -18,25 +18,9 @@
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#include "common.h"
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#include "mx27.h"
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static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
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OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
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OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
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OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
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OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
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OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
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OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
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OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
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OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
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OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
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OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
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OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
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{ /* sentinel */ }
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};
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static void __init imx27_dt_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table,
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imx27_auxdata_lookup, NULL);
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char * const imx27_dt_board_compat[] __initconst = {
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