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	drm/rockchip: vop2: Make overlay layer select register configuration take effect by vsync
Because the layer/window enable/disable is take effect by vsync, if the overlay configuration of these layers does not follow vsync and takes effect immediately instead, when multiple layers are dynamically enable/disable, inconsistent display contents may be seen on the screen. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250318062024.4555-1-andyshrk@163.com
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					 2 changed files with 5 additions and 1 deletions
				
			
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			@ -710,6 +710,7 @@ enum dst_factor_mode {
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#define VOP2_COLOR_KEY_MASK				BIT(31)
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#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL		GENMASK(31, 30)
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#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD		BIT(28)
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#define RK3568_OVL_CTRL__YUV_MODE(vp)			BIT(vp)
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			@ -2070,7 +2070,10 @@ static void rk3568_vop2_setup_layer_mixer(struct vop2_video_port *vp)
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	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
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	ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
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	ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
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	ovl_ctrl &= ~RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
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	ovl_ctrl &= ~RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL;
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	ovl_ctrl |= FIELD_PREP(RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL, vp->id);
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	if (vcstate->yuv_overlay)
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		ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);
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	else
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