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ARM: convert PCI defines to variables

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Convert PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM to variables to allow
multi-platform builds. This also removes the requirement for a platform to
have a mach/hardware.h.

The default values for i/o and mem are 0x1000 and 0x01000000, respectively.
Per Arnd Bergmann, other values are likely to be incorrect, but this commit
does not try to address that issue.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring 2011-06-28 21:16:13 -05:00
parent dc8d966bcc
commit c9d95fbe59
35 changed files with 57 additions and 110 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/include/asm/pci.h
View file

@ -6,7 +6,11 @@
#include <asm-generic/pci-bridge.h> #include <asm-generic/pci-bridge.h>
#include <asm/mach/pci.h> /* for pci_sys_data */ #include <asm/mach/pci.h> /* for pci_sys_data */
#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
extern unsigned long pcibios_min_io;
#define PCIBIOS_MIN_IO pcibios_min_io
extern unsigned long pcibios_min_mem;
#define PCIBIOS_MIN_MEM pcibios_min_mem
static inline int pcibios_assign_all_busses(void) static inline int pcibios_assign_all_busses(void)
{ {

21
arch/arm/mach-cns3xxx/include/mach/hardware.h
View file

@ -1,21 +0,0 @@
/*
* This file contains the hardware definitions of the Cavium Networks boards.
*
* Copyright 2003 ARM Limited.
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#include <asm/sizes.h>
/* macro to get at IO space when running virtually */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#endif

3
arch/arm/mach-cns3xxx/pcie.c
View file

@ -369,6 +369,9 @@ static int __init cns3xxx_pcie_init(void)
{ {
int i; int i;
pcibios_min_io = 0;
pcibios_min_mem = 0;
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
"imprecise external abort"); "imprecise external abort");

2
arch/arm/mach-dove/include/mach/hardware.h
View file

@ -11,8 +11,6 @@
#include "dove.h" #include "dove.h"
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE #define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE

2
arch/arm/mach-footbridge/dc21285.c
View file

@ -295,6 +295,8 @@ void __init dc21285_preinit(void)
unsigned int mem_size, mem_mask; unsigned int mem_size, mem_mask;
int cfn_mode; int cfn_mode;
pcibios_min_mem = 0x81000000;
mem_size = (unsigned int)high_memory - PAGE_OFFSET; mem_size = (unsigned int)high_memory - PAGE_OFFSET;
for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
if (mem_mask >= mem_size) if (mem_mask >= mem_size)

3
arch/arm/mach-footbridge/include/mach/hardware.h
View file

@ -100,7 +100,4 @@ extern unsigned int nw_gpio_read(void);
extern void nw_cpld_modify(unsigned int mask, unsigned int set); extern void nw_cpld_modify(unsigned int mask, unsigned int set);
#endif #endif
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x81000000
#endif #endif

3
arch/arm/mach-integrator/include/mach/hardware.h
View file

@ -34,9 +34,6 @@
#define PCIMEM_BASE PCI_MEMORY_VADDR #define PCIMEM_BASE PCI_MEMORY_VADDR
#define PCIBIOS_MIN_IO 0x6000
#define PCIBIOS_MIN_MEM 0x00100000
/* macro to get at IO space when running virtually */ /* macro to get at IO space when running virtually */
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)

3
arch/arm/mach-integrator/pci_v3.c
View file

@ -502,6 +502,9 @@ void __init pci_v3_preinit(void)
unsigned int temp; unsigned int temp;
int ret; int ret;
pcibios_min_io = 0x6000;
pcibios_min_mem = 0x00100000;
/* /*
* Hook in our fault handler for PCI errors * Hook in our fault handler for PCI errors
*/ */

5
arch/arm/mach-iop13xx/include/mach/hardware.h
View file

@ -3,15 +3,10 @@
#include <asm/types.h> #include <asm/types.h>
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
extern unsigned long iop13xx_pcibios_min_io;
extern unsigned long iop13xx_pcibios_min_mem;
extern u16 iop13xx_dev_id(void); extern u16 iop13xx_dev_id(void);
extern void iop13xx_set_atu_mmr_bases(void); extern void iop13xx_set_atu_mmr_bases(void);
#endif #endif
#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
/* /*
* Generic chipset bits * Generic chipset bits
* *

5
arch/arm/mach-iop13xx/pci.c
View file

@ -39,8 +39,6 @@ u32 iop13xx_atue_mem_base;
u32 iop13xx_atux_mem_base; u32 iop13xx_atux_mem_base;
size_t iop13xx_atue_mem_size; size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size; size_t iop13xx_atux_mem_size;
unsigned long iop13xx_pcibios_min_io = 0;
unsigned long iop13xx_pcibios_min_mem = 0;
EXPORT_SYMBOL(iop13xx_atue_mem_base); EXPORT_SYMBOL(iop13xx_atue_mem_base);
EXPORT_SYMBOL(iop13xx_atux_mem_base); EXPORT_SYMBOL(iop13xx_atux_mem_base);
@ -971,7 +969,8 @@ void __init iop13xx_pci_init(void)
__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
/* Setup the Min Address for PCI memory... */ /* Setup the Min Address for PCI memory... */
iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; pcibios_min_io = 0;
pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
/* if Linux is given control of an ATU /* if Linux is given control of an ATU
* clear out its prior configuration, * clear out its prior configuration,

2
arch/arm/mach-iop32x/include/mach/hardware.h
View file

@ -18,8 +18,6 @@
* but when we read them, we convert them to virtual addresses. See * but when we read them, we convert them to virtual addresses. See
* arch/arm/plat-iop/pci.c. * arch/arm/plat-iop/pci.c.
*/ */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
void iop32x_init_irq(void); void iop32x_init_irq(void);

2
arch/arm/mach-iop33x/include/mach/hardware.h
View file

@ -18,8 +18,6 @@
* but when we read them, we convert them to virtual addresses. See * but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop3xx/iop3xx-pci.c * arch/arm/mach-iop3xx/iop3xx-pci.c
*/ */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
void iop33x_init_irq(void); void iop33x_init_irq(void);

6
arch/arm/mach-ixp2000/include/mach/hardware.h
View file

@ -19,12 +19,6 @@
#ifndef __ASM_ARCH_HARDWARE_H__ #ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__ #define __ASM_ARCH_HARDWARE_H__
/*
* This needs to be platform-specific?
*/
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#include "ixp2000-regs.h" /* Chipset Registers */ #include "ixp2000-regs.h" /* Chipset Registers */
/* /*

3
arch/arm/mach-ixp2000/pci.c
View file

@ -198,6 +198,9 @@ ixp2000_pci_preinit(void)
{ {
pci_set_flags(0); pci_set_flags(0);
pcibios_min_io = 0;
pcibios_min_mem = 0;
#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO #ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
/* /*
* Configure the PCI unit to properly byteswap I/O transactions, * Configure the PCI unit to properly byteswap I/O transactions,

2
arch/arm/mach-ixp23xx/include/mach/hardware.h
View file

@ -15,8 +15,6 @@
#define __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H
/* PCI IO info */ /* PCI IO info */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0xe0000000
#include "ixp23xx.h" #include "ixp23xx.h"

3
arch/arm/mach-ixp23xx/pci.c
View file

@ -227,6 +227,9 @@ static void __init ixp23xx_pci_common_init(void)
void __init ixp23xx_pci_preinit(void) void __init ixp23xx_pci_preinit(void)
{ {
pcibios_min_io = 0;
pcibios_min_mem = 0xe0000000;
pci_set_flags(0); pci_set_flags(0);
ixp23xx_pci_common_init(); ixp23xx_pci_common_init();

5
arch/arm/mach-ixp4xx/common-pci.c
View file

@ -346,6 +346,11 @@ void __init ixp4xx_pci_preinit(void)
{ {
unsigned long cpuid = read_cpuid_id(); unsigned long cpuid = read_cpuid_id();
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
#else
pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
#endif
/* /*
* Determine which PCI read method to use. * Determine which PCI read method to use.
* Rev 0 IXP425 requires workaround. * Rev 0 IXP425 requires workaround.

3
arch/arm/mach-ixp4xx/include/mach/hardware.h
View file

@ -17,12 +17,9 @@
#ifndef __ASM_ARCH_HARDWARE_H__ #ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__ #define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
#ifdef CONFIG_IXP4XX_INDIRECT_PCI #ifdef CONFIG_IXP4XX_INDIRECT_PCI
#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4FFFFFFF #define PCIBIOS_MAX_MEM 0x4FFFFFFF
#else #else
#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4BFFFFFF #define PCIBIOS_MAX_MEM 0x4BFFFFFF
#endif #endif

1
arch/arm/mach-kirkwood/include/mach/hardware.h
View file

@ -11,7 +11,6 @@
#include "kirkwood.h" #include "kirkwood.h"
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */ #define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */

7
arch/arm/mach-ks8695/include/mach/hardware.h
View file

@ -42,11 +42,4 @@
#define KS8695_PCIIO_PA 0x80000000 #define KS8695_PCIIO_PA 0x80000000
#define KS8695_PCIIO_SIZE SZ_64K #define KS8695_PCIIO_SIZE SZ_64K
/*
* PCI support
*/
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0
#endif #endif

3
arch/arm/mach-ks8695/pci.c
View file

@ -317,6 +317,9 @@ void __init ks8695_init_pci(struct ks8695_pci_cfg *cfg)
return; return;
} }
pcibios_min_io = 0;
pcibios_min_mem = 0;
printk(KERN_INFO "PCI: Initialising\n"); printk(KERN_INFO "PCI: Initialising\n");
ks8695_show_pciregs(); ks8695_show_pciregs();

2
arch/arm/mach-mv78xx0/include/mach/hardware.h
View file

@ -11,8 +11,6 @@
#include "mv78xx0.h" #include "mv78xx0.h"
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */ #define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */

2
arch/arm/mach-orion5x/include/mach/hardware.h
View file

@ -11,8 +11,6 @@
#include "orion5x.h" #include "orion5x.h"
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE #define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE

3
arch/arm/mach-pxa/cm-x2xx-pci.c
View file

@ -125,6 +125,9 @@ static void cmx2xx_pci_preinit(void)
{ {
pr_info("Initializing CM-X2XX PCI subsystem\n"); pr_info("Initializing CM-X2XX PCI subsystem\n");
pcibios_min_io = 0;
pcibios_min_mem = 0;
__raw_writel(0x800, IT8152_PCI_CFG_ADDR); __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
pr_info("PCI Bridge found.\n"); pr_info("PCI Bridge found.\n");

2
arch/arm/mach-pxa/include/mach/hardware.h
View file

@ -337,8 +337,6 @@ extern unsigned long get_clock_tick_rate(void);
#endif #endif
#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0
#define ARCH_HAS_DMA_SET_COHERENT_MASK #define ARCH_HAS_DMA_SET_COHERENT_MASK
#endif #endif

7
arch/arm/mach-sa1100/include/mach/hardware.h
View file

@ -76,11 +76,4 @@ static inline unsigned long get_clock_tick_rate(void)
#include "SA-1101.h" #include "SA-1101.h"
#endif #endif
#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0
#define HAVE_ARCH_PCI_SET_DMA_MASK 1
#endif
#endif /* _ASM_ARCH_HARDWARE_H */ #endif /* _ASM_ARCH_HARDWARE_H */

3
arch/arm/mach-sa1100/pci-nanoengine.c
View file

@ -252,6 +252,9 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
{ {
int ret = 0; int ret = 0;
pcibios_min_io = 0;
pcibios_min_mem = 0;
if (nr == 0) { if (nr == 0) {
sys->mem_offset = NANO_PCI_MEM_RW_PHYS; sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
sys->io_offset = 0x400; sys->io_offset = 0x400;

2
arch/arm/mach-shark/include/mach/hardware.h
View file

@ -12,8 +12,6 @@
#define UNCACHEABLE_ADDR 0xdf010000 #define UNCACHEABLE_ADDR 0xdf010000
#define PCIBIOS_MIN_IO 0x6000
#define PCIBIOS_MIN_MEM 0x50000000
#define PCIMEM_BASE 0xe8000000 #define PCIMEM_BASE 0xe8000000
#endif #endif

10
arch/arm/mach-shark/pci.c
View file

@ -37,8 +37,14 @@ static struct hw_pci shark_pci __initdata = {
static int __init shark_pci_init(void) static int __init shark_pci_init(void)
{ {
if (machine_is_shark()) if (!machine_is_shark())
pci_common_init(&shark_pci); return;
pcibios_min_io = 0x6000;
pcibios_min_mem = 0x50000000;
pci_common_init(&shark_pci);
return 0; return 0;
} }

27
arch/arm/mach-tegra/include/mach/hardware.h
View file

@ -1,27 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/hardware.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_HARDWARE_H
#define __MACH_TEGRA_HARDWARE_H
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0
#endif

2
arch/arm/mach-tegra/pcie.c
View file

@ -912,6 +912,8 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
if (!(init_port0 || init_port1)) if (!(init_port0 || init_port1))
return -ENODEV; return -ENODEV;
pcibios_min_mem = 0;
err = tegra_pcie_get_resources(); err = tegra_pcie_get_resources();
if (err) if (err)
return err; return err;

4
arch/arm/mach-versatile/include/mach/hardware.h
View file

@ -30,10 +30,6 @@
#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
/* CIK guesswork */
#define PCIBIOS_MIN_IO 0x44000000
#define PCIBIOS_MIN_MEM 0x50000000
/* macro to get at IO space when running virtually */ /* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)

3
arch/arm/mach-versatile/pci.c
View file

@ -311,6 +311,9 @@ struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
void __init pci_versatile_preinit(void) void __init pci_versatile_preinit(void)
{ {
pcibios_min_io = 0x44000000;
pcibios_min_mem = 0x50000000;
__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1); __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2); __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);

7
arch/arm/mm/iomap.c
View file

@ -8,7 +8,6 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/pci.h>
#ifdef __io #ifdef __io
void __iomem *ioport_map(unsigned long port, unsigned int nr) void __iomem *ioport_map(unsigned long port, unsigned int nr)
@ -24,6 +23,12 @@ EXPORT_SYMBOL(ioport_unmap);
#endif #endif
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
unsigned long pcibios_min_io = 0x1000;
EXPORT_SYMBOL(pcibios_min_io);
unsigned long pcibios_min_mem = 0x01000000;
EXPORT_SYMBOL(pcibios_min_mem);
unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC; unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
EXPORT_SYMBOL(pci_flags); EXPORT_SYMBOL(pci_flags);

3
arch/arm/plat-iop/pci.c
View file

@ -374,6 +374,9 @@ void __init iop3xx_pci_preinit_cond(void)
void __init iop3xx_pci_preinit(void) void __init iop3xx_pci_preinit(void)
{ {
pcibios_min_io = 0;
pcibios_min_mem = 0;
iop3xx_atu_disable(); iop3xx_atu_disable();
iop3xx_atu_setup(); iop3xx_atu_setup();
iop3xx_atu_debug(); iop3xx_atu_debug();