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x86/irq: Convert IOAPIC to use hierarchical irqdomain interfaces
Convert IOAPIC driver to support and use hierarchical irqdomain interfaces. It's a little big, but would break bisecting if we split it into multiple patches. Fold in a patch from Andy Shevchenko <andriy.shevchenko@linux.intel.com> to make it bisectable. http://lkml.org/lkml/2014/12/10/622 Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Tested-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: sfi-devel@simplefirmware.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Len Brown <len.brown@intel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: David Rientjes <rientjes@google.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Link: http://lkml.kernel.org/r/1428905519-23704-38-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Jiang Liu
Thomas Gleixner
parent
96ed44b2d5
commit
d32932d02e
8 changed files with 241 additions and 138 deletions
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@ -412,11 +412,6 @@ static int mp_register_gsi(struct device *dev, u32 gsi, int trigger,
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trigger = trigger == ACPI_EDGE_SENSITIVE ? 0 : 1;
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polarity = polarity == ACPI_ACTIVE_HIGH ? 0 : 1;
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node = dev ? dev_to_node(dev) : NUMA_NO_NODE;
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if (mp_set_gsi_attr(gsi, trigger, polarity, node)) {
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pr_warn("Failed to set pin attr for GSI%d\n", gsi);
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return -1;
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}
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ioapic_set_alloc_attr(&info, node, trigger, polarity);
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irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
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if (irq < 0)
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@ -442,8 +437,10 @@ static void mp_unregister_gsi(u32 gsi)
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}
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static struct irq_domain_ops acpi_irqdomain_ops = {
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.map = mp_irqdomain_map,
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.unmap = mp_irqdomain_unmap,
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.alloc = mp_irqdomain_alloc,
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.free = mp_irqdomain_free,
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.activate = mp_irqdomain_activate,
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.deactivate = mp_irqdomain_deactivate,
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};
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static int __init
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@ -142,6 +142,11 @@ u32 mp_pin_to_gsi(int ioapic, int pin)
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return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
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}
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static inline bool mp_is_legacy_irq(int irq)
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{
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return irq >= 0 && irq < nr_legacy_irqs();
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}
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/*
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* Initialize all legacy IRQs and all pins on the first IOAPIC
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* if we have legacy interrupt controller. Kernel boot option "pirq="
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@ -152,7 +157,7 @@ static inline int mp_init_irq_at_boot(int ioapic, int irq)
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if (!nr_legacy_irqs())
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return 0;
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return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs());
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return ioapic == 0 || mp_is_legacy_irq(irq);
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}
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static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
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@ -231,7 +236,7 @@ struct irq_pin_list {
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static struct irq_pin_list *alloc_irq_pin_list(int node)
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{
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return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
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return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
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}
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static void alloc_ioapic_saved_registers(int idx)
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@ -560,6 +565,17 @@ void native_eoi_ioapic_pin(int apic, int pin, int vector)
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}
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}
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void eoi_ioapic_pin(int vector, struct irq_cfg *cfg)
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{
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unsigned long flags;
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struct irq_pin_list *entry;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, cfg->irq_2_pin)
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native_eoi_ioapic_pin(entry->apic, entry->pin, vector);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
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{
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struct irq_pin_list *entry;
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@ -603,9 +619,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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entry.trigger = IOAPIC_LEVEL;
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ioapic_write_entry(apic, pin, entry);
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}
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
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native_eoi_ioapic_pin(apic, pin, entry.vector);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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@ -1023,95 +1038,121 @@ static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
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data->polarity == info->ioapic_polarity;
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}
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static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin,
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static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
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struct irq_alloc_info *info)
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{
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bool legacy = false;
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int irq = -1;
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int ioapic = mp_irqdomain_ioapic_idx(domain);
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int type = ioapics[ioapic].irqdomain_cfg.type;
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switch (type) {
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case IOAPIC_DOMAIN_LEGACY:
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/*
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* Dynamically allocate IRQ number for non-ISA IRQs in the first 16
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* GSIs on some weird platforms.
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* Dynamically allocate IRQ number for non-ISA IRQs in the first
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* 16 GSIs on some weird platforms.
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*/
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if (gsi < nr_legacy_irqs())
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irq = irq_create_mapping(domain, pin);
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else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
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if (!ioapic_initialized || gsi >= nr_legacy_irqs())
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irq = gsi;
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legacy = mp_is_legacy_irq(irq);
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break;
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case IOAPIC_DOMAIN_STRICT:
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if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
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irq = gsi;
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irq = gsi;
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break;
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case IOAPIC_DOMAIN_DYNAMIC:
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irq = irq_create_mapping(domain, pin);
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break;
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default:
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WARN(1, "ioapic: unknown irqdomain type %d\n", type);
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break;
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return -1;
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}
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return irq > 0 ? irq : -1;
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return __irq_domain_alloc_irqs(domain, irq, 1,
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ioapic_alloc_attr_node(info),
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info, legacy);
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}
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/*
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* Need special handling for ISA IRQs because there may be multiple IOAPIC pins
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* sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
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* between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
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* used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
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* When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
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* some BIOSes may use MP Interrupt Source records to override IRQ numbers for
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* PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
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* multiple pins sharing the same legacy IRQ number when ACPI is disabled.
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*/
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static int alloc_isa_irq_from_domain(struct irq_domain *domain,
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int irq, int ioapic, int pin,
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struct irq_alloc_info *info)
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{
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struct mp_chip_data *data;
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struct irq_data *irq_data = irq_get_irq_data(irq);
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int node = ioapic_alloc_attr_node(info);
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/*
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* Legacy ISA IRQ has already been allocated, just add pin to
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* the pin list assoicated with this IRQ and program the IOAPIC
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* entry. The IOAPIC entry
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*/
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if (irq_data && irq_data->parent_data) {
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struct irq_cfg *cfg = irqd_cfg(irq_data);
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if (!mp_check_pin_attr(irq, info))
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return -EBUSY;
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if (__add_pin_to_irq_node(cfg, node, ioapic, info->ioapic_pin))
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return -ENOMEM;
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} else {
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irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
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if (irq >= 0) {
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irq_data = irq_domain_get_irq_data(domain, irq);
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data = irq_data->chip_data;
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data->isa_irq = true;
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}
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}
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return irq;
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}
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static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
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unsigned int flags, struct irq_alloc_info *info)
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{
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int irq;
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bool legacy = false;
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struct irq_alloc_info tmp;
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struct mp_chip_data *data;
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struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
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struct mp_pin_info *pinfo = mp_pin_info(ioapic, pin);
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if (!domain)
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return -1;
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return -ENOSYS;
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mutex_lock(&ioapic_mutex);
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/*
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* Don't use irqdomain to manage ISA IRQs because there may be
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* multiple IOAPIC pins sharing the same ISA IRQ number and
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* irqdomain only supports 1:1 mapping between IOAPIC pin and
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* IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
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* for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
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* When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
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* available, and some BIOSes may use MP Interrupt Source records
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* to override IRQ numbers for PIRQs instead of reprogramming
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* the interrupt routing logic. Thus there may be multiple pins
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* sharing the same legacy IRQ number when ACPI is disabled.
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*/
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if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
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irq = mp_irqs[idx].srcbusirq;
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if (flags & IOAPIC_MAP_ALLOC) {
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if (pinfo->count == 0 &&
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mp_irqdomain_map(domain, irq, pin) != 0)
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irq = -1;
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legacy = mp_is_legacy_irq(irq);
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}
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/* special handling for timer IRQ0 */
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mutex_lock(&ioapic_mutex);
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if (!(flags & IOAPIC_MAP_ALLOC)) {
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if (!legacy) {
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irq = irq_find_mapping(domain, pin);
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if (irq == 0)
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pinfo->count++;
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irq = -ENOENT;
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}
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} else {
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irq = irq_find_mapping(domain, pin);
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if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC))
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irq = alloc_irq_from_domain(domain, gsi, pin, info);
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ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
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if (legacy)
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irq = alloc_isa_irq_from_domain(domain, irq,
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ioapic, pin, &tmp);
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else if ((irq = irq_find_mapping(domain, pin)) == 0)
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irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
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else if (!mp_check_pin_attr(irq, &tmp))
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irq = -EBUSY;
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if (irq >= 0) {
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data = irq_get_chip_data(irq);
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data->count++;
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}
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}
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if (flags & IOAPIC_MAP_ALLOC) {
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/* special handling for legacy IRQs */
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if (irq < nr_legacy_irqs() && pinfo->count == 1 &&
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mp_irqdomain_map(domain, irq, pin) != 0)
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irq = -1;
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if (irq > 0)
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pinfo->count++;
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else if (pinfo->count == 0)
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pinfo->set = 0;
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}
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mutex_unlock(&ioapic_mutex);
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return irq > 0 ? irq : -1;
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return irq;
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}
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static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
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@ -1166,26 +1207,19 @@ int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
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void mp_unmap_irq(int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct mp_pin_info *info;
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int ioapic, pin;
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struct irq_data *irq_data = irq_get_irq_data(irq);
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struct mp_chip_data *data;
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if (!data || !data->domain)
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if (!irq_data || !irq_data->domain)
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return;
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ioapic = (int)(long)data->domain->host_data;
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pin = (int)data->hwirq;
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info = mp_pin_info(ioapic, pin);
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data = irq_data->chip_data;
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if (!data || data->isa_irq)
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return;
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mutex_lock(&ioapic_mutex);
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if (--info->count == 0) {
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info->set = 0;
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if (irq < nr_legacy_irqs() &&
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ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY)
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mp_irqdomain_unmap(data->domain, irq);
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else
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irq_dispose_mapping(irq);
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}
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if (--data->count == 0)
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irq_domain_free_irqs(irq, 1);
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mutex_unlock(&ioapic_mutex);
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}
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@ -1252,7 +1286,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
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}
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EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
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static struct irq_chip ioapic_chip;
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static struct irq_chip ioapic_chip, ioapic_ir_chip;
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#ifdef CONFIG_X86_32
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static inline int IO_APIC_irq_trigger(int irq)
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@ -1595,7 +1629,7 @@ void __init print_IO_APICs(void)
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struct irq_pin_list *entry;
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chip = irq_get_chip(irq);
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if (chip != &ioapic_chip)
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if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
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continue;
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cfg = irq_cfg(irq);
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@ -2057,12 +2091,12 @@ static inline void ioapic_irqd_unmask(struct irq_data *data,
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}
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#endif
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static void ack_ioapic_level(struct irq_data *data)
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static void ioapic_ack_level(struct irq_data *data)
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{
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struct irq_cfg *cfg = irqd_cfg(data);
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int i, irq = data->irq;
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unsigned long v;
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bool masked;
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int i;
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irq_complete_move(cfg);
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masked = ioapic_irqd_mask(data, cfg);
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@ -2117,22 +2151,70 @@ static void ack_ioapic_level(struct irq_data *data)
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*/
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if (!(v & (1 << (i & 0x1f)))) {
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atomic_inc(&irq_mis_count);
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eoi_ioapic_irq(irq, cfg);
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eoi_ioapic_pin(cfg->vector, cfg);
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}
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ioapic_irqd_unmask(data, cfg, masked);
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}
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static void ioapic_ir_ack_level(struct irq_data *irq_data)
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{
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struct mp_chip_data *data = irq_data->chip_data;
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/*
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* Intr-remapping uses pin number as the virtual vector
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* in the RTE. Actual vector is programmed in
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* intr-remapping table entry. Hence for the io-apic
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* EOI we use the pin number.
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*/
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ack_APIC_irq();
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eoi_ioapic_pin(data->entry.vector, irqd_cfg(irq_data));
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}
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static int ioapic_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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struct irq_data *parent = irq_data->parent_data;
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struct mp_chip_data *data = irq_data->chip_data;
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unsigned int dest, irq = irq_data->irq;
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struct irq_cfg *cfg;
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unsigned long flags;
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
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cfg = irqd_cfg(irq_data);
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data->entry.dest = cfg->dest_apicid;
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data->entry.vector = cfg->vector;
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/* Only the high 8 bits are valid. */
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dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid);
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__target_IO_APIC_irq(irq, dest, cfg);
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}
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return ret;
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}
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static struct irq_chip ioapic_chip __read_mostly = {
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.name = "IO-APIC",
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.irq_startup = startup_ioapic_irq,
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.irq_mask = mask_ioapic_irq,
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.irq_unmask = unmask_ioapic_irq,
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.irq_ack = apic_ack_edge,
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.irq_eoi = ack_ioapic_level,
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.irq_set_affinity = native_ioapic_set_affinity,
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.irq_retrigger = apic_retrigger_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_eoi = ioapic_ack_level,
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.irq_set_affinity = ioapic_set_affinity,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
static struct irq_chip ioapic_ir_chip __read_mostly = {
|
||||
.name = "IR-IO-APIC",
|
||||
.irq_startup = startup_ioapic_irq,
|
||||
.irq_mask = mask_ioapic_irq,
|
||||
.irq_unmask = unmask_ioapic_irq,
|
||||
.irq_ack = irq_chip_ack_parent,
|
||||
.irq_eoi = ioapic_ir_ack_level,
|
||||
.irq_set_affinity = ioapic_set_affinity,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
|
|
@ -2265,6 +2347,24 @@ static int __init disable_timer_pin_setup(char *arg)
|
|||
}
|
||||
early_param("disable_timer_pin_1", disable_timer_pin_setup);
|
||||
|
||||
static int mp_alloc_timer_irq(int ioapic, int pin)
|
||||
{
|
||||
int irq = -1;
|
||||
struct irq_alloc_info info;
|
||||
struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
|
||||
|
||||
if (domain) {
|
||||
ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
|
||||
info.ioapic_id = mpc_ioapic_id(ioapic);
|
||||
info.ioapic_pin = pin;
|
||||
mutex_lock(&ioapic_mutex);
|
||||
irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
|
||||
mutex_unlock(&ioapic_mutex);
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
/*
|
||||
* This code may look a bit paranoid, but it's supposed to cooperate with
|
||||
* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
|
||||
|
|
@ -2287,7 +2387,6 @@ static inline void __init check_timer(void)
|
|||
* get/set the timer IRQ vector:
|
||||
*/
|
||||
legacy_pic->mask(0);
|
||||
assign_irq_vector(0, cfg, apic->target_cpus());
|
||||
|
||||
/*
|
||||
* As IRQ0 is to be enabled in the 8259A, the virtual
|
||||
|
|
@ -2328,15 +2427,12 @@ static inline void __init check_timer(void)
|
|||
}
|
||||
|
||||
if (pin1 != -1) {
|
||||
/*
|
||||
* Ok, does IRQ0 through the IOAPIC work?
|
||||
*/
|
||||
/* Ok, does IRQ0 through the IOAPIC work? */
|
||||
if (no_pin1) {
|
||||
add_pin_to_irq_node(cfg, node, apic1, pin1);
|
||||
setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
|
||||
mp_alloc_timer_irq(apic1, pin1);
|
||||
} else {
|
||||
/* for edge trigger, setup_ioapic_irq already
|
||||
* leave it unmasked.
|
||||
/*
|
||||
* for edge trigger, it's already unmasked,
|
||||
* so only need to unmask if it is level-trigger
|
||||
* do we really have level trigger timer?
|
||||
*/
|
||||
|
|
@ -2345,6 +2441,7 @@ static inline void __init check_timer(void)
|
|||
if (idx != -1 && irq_trigger(idx))
|
||||
unmask_ioapic(cfg);
|
||||
}
|
||||
irq_domain_activate_irq(irq_get_irq_data(0));
|
||||
if (timer_irq_works()) {
|
||||
if (disable_timer_pin_1 > 0)
|
||||
clear_IO_APIC_pin(0, pin1);
|
||||
|
|
@ -2365,7 +2462,7 @@ static inline void __init check_timer(void)
|
|||
* legacy devices should be connected to IO APIC #0
|
||||
*/
|
||||
replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
|
||||
setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
|
||||
irq_domain_activate_irq(irq_get_irq_data(0));
|
||||
legacy_pic->unmask(0);
|
||||
if (timer_irq_works()) {
|
||||
apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
|
||||
|
|
@ -2443,6 +2540,8 @@ static inline void __init check_timer(void)
|
|||
static int mp_irqdomain_create(int ioapic)
|
||||
{
|
||||
size_t size;
|
||||
struct irq_alloc_info info;
|
||||
struct irq_domain *parent;
|
||||
int hwirqs = mp_ioapic_pin_count(ioapic);
|
||||
struct ioapic *ip = &ioapics[ioapic];
|
||||
struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
|
||||
|
|
@ -2456,9 +2555,18 @@ static int mp_irqdomain_create(int ioapic)
|
|||
if (cfg->type == IOAPIC_DOMAIN_INVALID)
|
||||
return 0;
|
||||
|
||||
init_irq_alloc_info(&info, NULL);
|
||||
info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
|
||||
info.ioapic_id = mpc_ioapic_id(ioapic);
|
||||
parent = irq_remapping_get_ir_irq_domain(&info);
|
||||
if (!parent)
|
||||
parent = x86_vector_domain;
|
||||
|
||||
ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
|
||||
(void *)(long)ioapic);
|
||||
if(!ip->irqdomain) {
|
||||
if (ip->irqdomain) {
|
||||
ip->irqdomain->parent = parent;
|
||||
} else {
|
||||
kfree(ip->pin_info);
|
||||
ip->pin_info = NULL;
|
||||
return -ENOMEM;
|
||||
|
|
@ -3072,7 +3180,6 @@ int mp_unregister_ioapic(u32 gsi_base)
|
|||
{
|
||||
int ioapic, pin;
|
||||
int found = 0;
|
||||
struct mp_pin_info *pin_info;
|
||||
|
||||
for_each_ioapic(ioapic)
|
||||
if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
|
||||
|
|
@ -3085,11 +3192,17 @@ int mp_unregister_ioapic(u32 gsi_base)
|
|||
}
|
||||
|
||||
for_each_pin(ioapic, pin) {
|
||||
pin_info = mp_pin_info(ioapic, pin);
|
||||
if (pin_info->count) {
|
||||
pr_warn("pin%d on IOAPIC%d is still in use.\n",
|
||||
pin, ioapic);
|
||||
return -EBUSY;
|
||||
u32 gsi = mp_pin_to_gsi(ioapic, pin);
|
||||
int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
|
||||
struct mp_chip_data *data;
|
||||
|
||||
if (irq >= 0) {
|
||||
data = irq_get_chip_data(irq);
|
||||
if (data && data->count) {
|
||||
pr_warn("pin%d on IOAPIC%d is still in use.\n",
|
||||
pin, ioapic);
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3241,7 +3354,8 @@ int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
|
|||
}
|
||||
|
||||
irq_data->hwirq = info->ioapic_pin;
|
||||
irq_data->chip = &ioapic_chip;
|
||||
irq_data->chip = (domain->parent == x86_vector_domain) ?
|
||||
&ioapic_chip : &ioapic_ir_chip;
|
||||
irq_data->chip_data = data;
|
||||
mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
|
||||
|
||||
|
|
|
|||
|
|
@ -196,38 +196,31 @@ static struct of_ioapic_type of_ioapic_type[] =
|
|||
},
|
||||
};
|
||||
|
||||
static int ioapic_xlate(struct irq_domain *domain,
|
||||
struct device_node *controller,
|
||||
const u32 *intspec, u32 intsize,
|
||||
irq_hw_number_t *out_hwirq, u32 *out_type)
|
||||
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs, void *arg)
|
||||
{
|
||||
struct of_phandle_args *irq_data = (void *)arg;
|
||||
struct of_ioapic_type *it;
|
||||
u32 line, idx, gsi;
|
||||
struct irq_alloc_info tmp;
|
||||
|
||||
if (WARN_ON(intsize < 2))
|
||||
if (WARN_ON(irq_data->args_count < 2))
|
||||
return -EINVAL;
|
||||
if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
|
||||
return -EINVAL;
|
||||
|
||||
line = intspec[0];
|
||||
it = &of_ioapic_type[irq_data->args[1]];
|
||||
ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
|
||||
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
|
||||
tmp.ioapic_pin = irq_data->args[0];
|
||||
|
||||
if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
|
||||
return -EINVAL;
|
||||
|
||||
it = &of_ioapic_type[intspec[1]];
|
||||
|
||||
idx = (u32)(long)domain->host_data;
|
||||
gsi = mp_pin_to_gsi(idx, line);
|
||||
if (mp_set_gsi_attr(gsi, it->trigger, it->polarity, cpu_to_node(0)))
|
||||
return -EBUSY;
|
||||
|
||||
*out_hwirq = line;
|
||||
*out_type = it->out_type;
|
||||
return 0;
|
||||
return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
|
||||
}
|
||||
|
||||
const struct irq_domain_ops ioapic_irq_domain_ops = {
|
||||
.map = mp_irqdomain_map,
|
||||
.unmap = mp_irqdomain_unmap,
|
||||
.xlate = ioapic_xlate,
|
||||
.alloc = dt_irqdomain_alloc,
|
||||
.free = mp_irqdomain_free,
|
||||
.activate = mp_irqdomain_activate,
|
||||
.deactivate = mp_irqdomain_deactivate,
|
||||
};
|
||||
|
||||
static void __init dtb_add_ioapic(struct device_node *dn)
|
||||
|
|
|
|||
|
|
@ -114,8 +114,10 @@ static void __init MP_bus_info(struct mpc_bus *m)
|
|||
}
|
||||
|
||||
static struct irq_domain_ops mp_ioapic_irqdomain_ops = {
|
||||
.map = mp_irqdomain_map,
|
||||
.unmap = mp_irqdomain_unmap,
|
||||
.alloc = mp_irqdomain_alloc,
|
||||
.free = mp_irqdomain_free,
|
||||
.activate = mp_irqdomain_activate,
|
||||
.deactivate = mp_irqdomain_deactivate,
|
||||
};
|
||||
|
||||
static void __init MP_ioapic_info(struct mpc_ioapic *m)
|
||||
|
|
|
|||
|
|
@ -224,8 +224,6 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
|
|||
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
|
||||
* IOAPIC RTE entries, so we just enable RTE for the device.
|
||||
*/
|
||||
if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
|
||||
return -EBUSY;
|
||||
if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
|
||||
return -EBUSY;
|
||||
|
||||
|
|
|
|||
|
|
@ -36,8 +36,7 @@ static int tangier_probe(struct platform_device *pdev)
|
|||
/* IOAPIC builds identity mapping between GSI and IRQ on MID */
|
||||
gsi = pdata->irq;
|
||||
ioapic_set_alloc_attr(&info, cpu_to_node(0), 1, 0);
|
||||
if (mp_set_gsi_attr(gsi, 1, 0, cpu_to_node(0)) ||
|
||||
mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info) <= 0) {
|
||||
if (mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info) <= 0) {
|
||||
dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n",
|
||||
gsi);
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -469,10 +469,7 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
|||
}
|
||||
|
||||
ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 1, polarity);
|
||||
ret = mp_set_gsi_attr(irq, 1, polarity, NUMA_NO_NODE);
|
||||
if (ret == 0)
|
||||
ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC,
|
||||
&info);
|
||||
ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC, &info);
|
||||
WARN_ON(ret < 0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,10 @@ static int __init sfi_parse_cpus(struct sfi_table_header *table)
|
|||
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
static struct irq_domain_ops sfi_ioapic_irqdomain_ops = {
|
||||
.map = mp_irqdomain_map,
|
||||
.alloc = mp_irqdomain_alloc,
|
||||
.free = mp_irqdomain_free,
|
||||
.activate = mp_irqdomain_activate,
|
||||
.deactivate = mp_irqdomain_deactivate,
|
||||
};
|
||||
|
||||
static int __init sfi_parse_ioapic(struct sfi_table_header *table)
|
||||
|
|
|
|||
Loading…
Reference in a new issue