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synced 2025-11-04 02:30:34 +02:00
EDAC, altera: Combine Stratix10 and Arria10 probe functions
On Stratix10, the ECC offsets are similar to the existing Arria10 functions and this can be leveraged to simplify the EDAC driver as follows: 1. Fold Stratix10 specifics into Arria10 structures and functions. 2. Implement the Stratix10 System Manager register accesses using a custom regmap to allow use with the Arria10 System Manager regmaps. 3. Stratix10 double bit errors are implemented as SError instead of interrupts so use a panic notifier. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: dinguyen@kernel.org Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: mchehab@kernel.org Cc: devicetree@vger.kernel.org Cc: linux-edac@vger.kernel.org Link: https://lkml.kernel.org/r/1537883342-30180-3-git-send-email-thor.thayer@linux.intel.com
This commit is contained in:
Thor Thayer
Borislav Petkov
parent
3ce078ffe2
commit
d5fc912556
2 changed files with 90 additions and 183 deletions
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@ -2146,6 +2146,35 @@ static const struct irq_domain_ops a10_eccmgr_ic_ops = {
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.xlate = irq_domain_xlate_twocell,
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};
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/************** Stratix 10 EDAC Double Bit Error Handler ************/
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#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
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/*
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* The double bit error is handled through SError which is fatal. This is
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* called as a panic notifier to printout ECC error info as part of the panic.
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*/
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static int s10_edac_dberr_handler(struct notifier_block *this,
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unsigned long event, void *ptr)
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{
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struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
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int err_addr, dberror;
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regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
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&dberror);
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regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
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if (dberror & S10_DDR0_IRQ_MASK) {
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regmap_read(edac->ecc_mgr_map, S10_DERRADDR_OFST, &err_addr);
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regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
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err_addr);
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edac_printk(KERN_ERR, EDAC_MC,
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"EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
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err_addr);
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}
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return NOTIFY_DONE;
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}
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/****************** Arria 10 EDAC Probe Function *********************/
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static int altr_edac_a10_probe(struct platform_device *pdev)
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{
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struct altr_arria10_edac *edac;
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@ -2159,8 +2188,33 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, edac);
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INIT_LIST_HEAD(&edac->a10_ecc_devices);
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edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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if (socfpga_is_a10()) {
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edac->ecc_mgr_map =
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syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"altr,sysmgr-syscon");
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} else {
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struct device_node *sysmgr_np;
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struct resource res;
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void __iomem *base;
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sysmgr_np = of_parse_phandle(pdev->dev.of_node,
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"altr,sysmgr-syscon", 0);
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if (!sysmgr_np) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to find altr,sysmgr-syscon\n");
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return -ENODEV;
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}
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if (of_address_to_resource(sysmgr_np, 0, &res))
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return -ENOMEM;
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/* Need physical address for SMCC call */
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base = (void __iomem *)res.start;
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edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL, base,
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&s10_sdram_regmap_cfg);
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}
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if (IS_ERR(edac->ecc_mgr_map)) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to get syscon altr,sysmgr-syscon\n");
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@ -2187,14 +2241,38 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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altr_edac_a10_irq_handler,
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edac);
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edac->db_irq = platform_get_irq(pdev, 1);
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if (edac->db_irq < 0) {
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dev_err(&pdev->dev, "No DBERR IRQ resource\n");
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return edac->db_irq;
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if (socfpga_is_a10()) {
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edac->db_irq = platform_get_irq(pdev, 1);
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if (edac->db_irq < 0) {
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dev_err(&pdev->dev, "No DBERR IRQ resource\n");
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return edac->db_irq;
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}
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irq_set_chained_handler_and_data(edac->db_irq,
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altr_edac_a10_irq_handler,
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edac);
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} else {
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int dberror, err_addr;
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edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
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atomic_notifier_chain_register(&panic_notifier_list,
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&edac->panic_notifier);
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/* Printout a message if uncorrectable error previously. */
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regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
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&dberror);
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if (dberror) {
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regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
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&err_addr);
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Previous Boot UE detected[0x%X] @ 0x%X\n",
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dberror, err_addr);
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/* Reset the sticky registers */
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regmap_write(edac->ecc_mgr_map,
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S10_SYSMGR_UE_VAL_OFST, 0);
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regmap_write(edac->ecc_mgr_map,
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S10_SYSMGR_UE_ADDR_OFST, 0);
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}
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}
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irq_set_chained_handler_and_data(edac->db_irq,
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altr_edac_a10_irq_handler,
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edac);
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for_each_child_of_node(pdev->dev.of_node, child) {
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if (!of_device_is_available(child))
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@ -2211,7 +2289,8 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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altr_edac_a10_device_add(edac, child);
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else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
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else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) ||
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(of_device_is_compatible(child, "altr,sdram-edac-s10")))
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of_platform_populate(pdev->dev.of_node,
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altr_sdram_ctrl_of_match,
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NULL, &pdev->dev);
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@ -2222,6 +2301,7 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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static const struct of_device_id altr_edac_a10_of_match[] = {
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{ .compatible = "altr,socfpga-a10-ecc-manager" },
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{ .compatible = "altr,socfpga-s10-ecc-manager" },
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
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@ -2235,171 +2315,6 @@ static struct platform_driver altr_edac_a10_driver = {
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};
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module_platform_driver(altr_edac_a10_driver);
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/************** Stratix 10 EDAC Device Controller Functions> ************/
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#define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m)
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/*
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* The double bit error is handled through SError which is fatal. This is
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* called as a panic notifier to printout ECC error info as part of the panic.
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*/
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static int s10_edac_dberr_handler(struct notifier_block *this,
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unsigned long event, void *ptr)
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{
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struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier);
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int err_addr, dberror;
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s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
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&dberror);
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/* Remember the UE Errors for a reboot */
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s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror);
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if (dberror & S10_DDR0_IRQ_MASK) {
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s10_protected_reg_read(edac, S10_DERRADDR_OFST, &err_addr);
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/* Remember the UE Error address */
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s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST,
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err_addr);
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edac_printk(KERN_ERR, EDAC_MC,
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"EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
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err_addr);
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}
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return NOTIFY_DONE;
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}
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static void altr_edac_s10_irq_handler(struct irq_desc *desc)
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{
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struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int irq = irq_desc_get_irq(desc);
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int bit, sm_offset, irq_status;
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sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
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chained_irq_enter(chip, desc);
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s10_protected_reg_read(NULL, sm_offset, &irq_status);
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for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
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irq = irq_linear_revmap(edac->domain, bit);
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if (irq)
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generic_handle_irq(irq);
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}
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chained_irq_exit(chip, desc);
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}
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static void s10_eccmgr_irq_mask(struct irq_data *d)
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{
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struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
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s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_SET_OFST,
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BIT(d->hwirq));
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}
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static void s10_eccmgr_irq_unmask(struct irq_data *d)
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{
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struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
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s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
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BIT(d->hwirq));
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}
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static int s10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct altr_stratix10_edac *edac = d->host_data;
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irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, edac);
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irq_set_noprobe(irq);
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return 0;
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}
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static const struct irq_domain_ops s10_eccmgr_ic_ops = {
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.map = s10_eccmgr_irqdomain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int altr_edac_s10_probe(struct platform_device *pdev)
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{
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struct altr_stratix10_edac *edac;
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struct device_node *child;
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int dberror, err_addr;
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edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
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if (!edac)
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return -ENOMEM;
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edac->dev = &pdev->dev;
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platform_set_drvdata(pdev, edac);
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INIT_LIST_HEAD(&edac->s10_ecc_devices);
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edac->irq_chip.name = pdev->dev.of_node->name;
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edac->irq_chip.irq_mask = s10_eccmgr_irq_mask;
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edac->irq_chip.irq_unmask = s10_eccmgr_irq_unmask;
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edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
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&s10_eccmgr_ic_ops, edac);
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if (!edac->domain) {
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dev_err(&pdev->dev, "Error adding IRQ domain\n");
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return -ENOMEM;
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}
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edac->sb_irq = platform_get_irq(pdev, 0);
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if (edac->sb_irq < 0) {
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dev_err(&pdev->dev, "No SBERR IRQ resource\n");
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return edac->sb_irq;
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}
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irq_set_chained_handler_and_data(edac->sb_irq,
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altr_edac_s10_irq_handler,
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edac);
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edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
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atomic_notifier_chain_register(&panic_notifier_list,
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&edac->panic_notifier);
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/* Printout a message if uncorrectable error previously. */
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s10_protected_reg_read(edac, S10_SYSMGR_UE_VAL_OFST, &dberror);
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if (dberror) {
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s10_protected_reg_read(edac, S10_SYSMGR_UE_ADDR_OFST,
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&err_addr);
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Previous Boot UE detected[0x%X] @ 0x%X\n",
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dberror, err_addr);
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/* Reset the sticky registers */
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s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, 0);
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s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, 0);
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}
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for_each_child_of_node(pdev->dev.of_node, child) {
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if (!of_device_is_available(child))
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continue;
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if (of_device_is_compatible(child, "altr,sdram-edac-s10"))
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of_platform_populate(pdev->dev.of_node,
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altr_sdram_ctrl_of_match,
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NULL, &pdev->dev);
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}
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return 0;
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}
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static const struct of_device_id altr_edac_s10_of_match[] = {
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{ .compatible = "altr,socfpga-s10-ecc-manager" },
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_edac_s10_of_match);
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static struct platform_driver altr_edac_s10_driver = {
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.probe = altr_edac_s10_probe,
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.driver = {
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.name = "socfpga_s10_ecc_manager",
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.of_match_table = altr_edac_s10_of_match,
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},
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};
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module_platform_driver(altr_edac_s10_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Thor Thayer");
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MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
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@ -370,6 +370,7 @@ struct altr_arria10_edac {
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struct irq_domain *domain;
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struct irq_chip irq_chip;
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struct list_head a10_ecc_devices;
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struct notifier_block panic_notifier;
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};
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/*
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@ -437,13 +438,4 @@ struct altr_arria10_edac {
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#define INTEL_SIP_SMC_REG_WRITE \
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INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
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struct altr_stratix10_edac {
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struct device *dev;
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int sb_irq;
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struct irq_domain *domain;
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struct irq_chip irq_chip;
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struct list_head s10_ecc_devices;
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struct notifier_block panic_notifier;
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};
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#endif /* #ifndef _ALTERA_EDAC_H */
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