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drm/mediatek: Add ETHDR support for MT8195
ETHDR is a part of ovl_adaptor. ETHDR is designed for HDR video and graphics conversion in the external display path. It handles multiple HDR input types and performs tone mapping, color space/color format conversion, and then combine different layers, output the required HDR or SDR signal to the subsequent display path. Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20230321121859.2355-3-nancy.lin@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
This commit is contained in:
Nancy.Lin
Chun-Kuang Hu
parent
64e352c9bd
commit
d886c0009b
5 changed files with 398 additions and 0 deletions
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@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
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mtk_drm_plane.o \
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mtk_dsi.o \
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mtk_dpi.o \
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mtk_ethdr.o \
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mtk_mdp_rdma.o
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obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
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@ -782,6 +782,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
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&mtk_dpi_driver,
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&mtk_drm_platform_driver,
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&mtk_dsi_driver,
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&mtk_ethdr_driver,
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&mtk_mdp_rdma_driver,
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};
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@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_ovl_driver;
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extern struct platform_driver mtk_disp_rdma_driver;
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extern struct platform_driver mtk_dpi_driver;
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extern struct platform_driver mtk_dsi_driver;
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extern struct platform_driver mtk_ethdr_driver;
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extern struct platform_driver mtk_mdp_rdma_driver;
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#endif /* MTK_DRM_DRV_H */
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370
drivers/gpu/drm/mediatek/mtk_ethdr.c
Normal file
370
drivers/gpu/drm/mediatek/mtk_ethdr.c
Normal file
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@ -0,0 +1,370 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include "mtk_drm_crtc.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_drv.h"
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#include "mtk_ethdr.h"
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#define MIX_INTEN 0x4
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#define MIX_FME_CPL_INTEN BIT(1)
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#define MIX_INTSTA 0x8
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#define MIX_EN 0xc
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#define MIX_RST 0x14
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#define MIX_ROI_SIZE 0x18
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#define MIX_DATAPATH_CON 0x1c
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#define OUTPUT_NO_RND BIT(3)
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#define SOURCE_RGB_SEL BIT(7)
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#define BACKGROUND_RELAY (4 << 9)
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#define MIX_ROI_BGCLR 0x20
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#define BGCLR_BLACK 0xff000000
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#define MIX_SRC_CON 0x24
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#define MIX_SRC_L0_EN BIT(0)
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#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
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#define NON_PREMULTI_SOURCE (2 << 12)
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#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
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#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
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#define MIX_FUNC_DCM0 0x120
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#define MIX_FUNC_DCM1 0x124
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#define MIX_FUNC_DCM_ENABLE 0xffffffff
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#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
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#define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
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#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
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#define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
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#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
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#define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
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#define MIXER_INX_MODE_BYPASS 0
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#define MIXER_INX_MODE_EVEN_EXTEND 1
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#define DEFAULT_9BIT_ALPHA 0x100
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#define MIXER_ALPHA_AEN BIT(8)
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#define MIXER_ALPHA 0xff
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#define ETHDR_CLK_NUM 13
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enum mtk_ethdr_comp_id {
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ETHDR_MIXER,
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ETHDR_VDO_FE0,
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ETHDR_VDO_FE1,
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ETHDR_GFX_FE0,
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ETHDR_GFX_FE1,
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ETHDR_VDO_BE,
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ETHDR_ADL_DS,
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ETHDR_ID_MAX
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};
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struct mtk_ethdr_comp {
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struct device *dev;
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void __iomem *regs;
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struct cmdq_client_reg cmdq_base;
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};
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struct mtk_ethdr {
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struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
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struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
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struct device *mmsys_dev;
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void (*vblank_cb)(void *data);
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void *vblank_cb_data;
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int irq;
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struct reset_control *reset_ctl;
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};
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static const char * const ethdr_clk_str[] = {
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"ethdr_top",
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"mixer",
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"vdo_fe0",
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"vdo_fe1",
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"gfx_fe0",
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"gfx_fe1",
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"vdo_be",
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"adl_ds",
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"vdo_fe0_async",
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"vdo_fe1_async",
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"gfx_fe0_async",
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"gfx_fe1_async",
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"vdo_be_async",
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};
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void mtk_ethdr_register_vblank_cb(struct device *dev,
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void (*vblank_cb)(void *),
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void *vblank_cb_data)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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priv->vblank_cb = vblank_cb;
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priv->vblank_cb_data = vblank_cb_data;
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}
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void mtk_ethdr_unregister_vblank_cb(struct device *dev)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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priv->vblank_cb = NULL;
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priv->vblank_cb_data = NULL;
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}
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void mtk_ethdr_enable_vblank(struct device *dev)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
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}
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void mtk_ethdr_disable_vblank(struct device *dev)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
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}
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static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
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{
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struct mtk_ethdr *priv = dev_id;
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writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
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if (!priv->vblank_cb)
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return IRQ_NONE;
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priv->vblank_cb(priv->vblank_cb_data);
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return IRQ_HANDLED;
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}
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void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
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struct mtk_plane_state *state,
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struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
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struct mtk_plane_pending_state *pending = &state->pending;
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unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
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unsigned int align_width = ALIGN_DOWN(pending->width, 2);
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unsigned int alpha_con = 0;
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dev_dbg(dev, "%s+ idx:%d", __func__, idx);
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if (idx >= 4)
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return;
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if (!pending->enable) {
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mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
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return;
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}
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if (state->base.fb && state->base.fb->format->has_alpha)
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alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
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mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true,
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DEFAULT_9BIT_ALPHA,
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pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
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MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);
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mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
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mixer->regs, MIX_L_SRC_SIZE(idx));
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mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
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mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
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0x1ff);
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mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
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BIT(idx));
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}
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void mtk_ethdr_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
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struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
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struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
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struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
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struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
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struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
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dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
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mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
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vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
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mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
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vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
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mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
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gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
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mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
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gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
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mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
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vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
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mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
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mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
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mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
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mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
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mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
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MIX_L_SRC_CON(0));
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mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
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MIX_L_SRC_CON(1));
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mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
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MIX_L_SRC_CON(2));
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mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
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MIX_L_SRC_CON(3));
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mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
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mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
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&mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
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mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
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MIX_SRC_CON, MIX_SRC_L0_EN);
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mtk_mmsys_hdr_config(priv->mmsys_dev, w / 2, h, cmdq_pkt);
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mtk_mmsys_mixer_in_channel_swap(priv->mmsys_dev, 4, 0, cmdq_pkt);
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}
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void mtk_ethdr_start(struct device *dev)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
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writel(1, mixer->regs + MIX_EN);
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}
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void mtk_ethdr_stop(struct device *dev)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
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writel(0, mixer->regs + MIX_EN);
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writel(1, mixer->regs + MIX_RST);
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reset_control_reset(priv->reset_ctl);
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writel(0, mixer->regs + MIX_RST);
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}
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int mtk_ethdr_clk_enable(struct device *dev)
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{
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int ret;
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
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if (ret)
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dev_err(dev,
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"ethdr_clk prepare enable failed\n");
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return ret;
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}
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void mtk_ethdr_clk_disable(struct device *dev)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
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}
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static int mtk_ethdr_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct mtk_ethdr *priv = dev_get_drvdata(dev);
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priv->mmsys_dev = data;
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return 0;
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}
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static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
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{
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}
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static const struct component_ops mtk_ethdr_component_ops = {
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.bind = mtk_ethdr_bind,
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.unbind = mtk_ethdr_unbind,
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};
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static int mtk_ethdr_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_ethdr *priv;
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int ret;
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int i;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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for (i = 0; i < ETHDR_ID_MAX; i++) {
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priv->ethdr_comp[i].dev = dev;
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priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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ret = cmdq_dev_get_client_reg(dev,
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&priv->ethdr_comp[i].cmdq_base, i);
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if (ret)
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dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
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#endif
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dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i);
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}
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for (i = 0; i < ETHDR_CLK_NUM; i++)
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priv->ethdr_clk[i].id = ethdr_clk_str[i];
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ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
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if (ret)
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return ret;
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priv->irq = platform_get_irq(pdev, 0);
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if (priv->irq < 0)
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priv->irq = 0;
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if (priv->irq) {
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ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
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IRQF_TRIGGER_NONE, dev_name(dev), priv);
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if (ret < 0) {
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dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
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return ret;
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}
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}
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priv->reset_ctl = devm_reset_control_array_get_optional_exclusive(dev);
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if (IS_ERR(priv->reset_ctl)) {
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dev_err_probe(dev, PTR_ERR(priv->reset_ctl), "cannot get ethdr reset control\n");
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return PTR_ERR(priv->reset_ctl);
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}
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platform_set_drvdata(pdev, priv);
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ret = component_add(dev, &mtk_ethdr_component_ops);
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if (ret)
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dev_notice(dev, "Failed to add component: %d\n", ret);
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return ret;
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}
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static int mtk_ethdr_remove(struct platform_device *pdev)
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{
|
||||
component_del(&pdev->dev, &mtk_ethdr_component_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
|
||||
{ .compatible = "mediatek,mt8195-disp-ethdr"},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
|
||||
|
||||
struct platform_driver mtk_ethdr_driver = {
|
||||
.probe = mtk_ethdr_probe,
|
||||
.remove = mtk_ethdr_remove,
|
||||
.driver = {
|
||||
.name = "mediatek-disp-ethdr",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mtk_ethdr_driver_dt_match,
|
||||
},
|
||||
};
|
||||
25
drivers/gpu/drm/mediatek/mtk_ethdr.h
Normal file
25
drivers/gpu/drm/mediatek/mtk_ethdr.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef __MTK_ETHDR_H__
|
||||
#define __MTK_ETHDR_H__
|
||||
|
||||
void mtk_ethdr_start(struct device *dev);
|
||||
void mtk_ethdr_stop(struct device *dev);
|
||||
int mtk_ethdr_clk_enable(struct device *dev);
|
||||
void mtk_ethdr_clk_disable(struct device *dev);
|
||||
void mtk_ethdr_config(struct device *dev, unsigned int w,
|
||||
unsigned int h, unsigned int vrefresh,
|
||||
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
|
||||
void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
|
||||
struct mtk_plane_state *state,
|
||||
struct cmdq_pkt *cmdq_pkt);
|
||||
void mtk_ethdr_register_vblank_cb(struct device *dev,
|
||||
void (*vblank_cb)(void *),
|
||||
void *vblank_cb_data);
|
||||
void mtk_ethdr_unregister_vblank_cb(struct device *dev);
|
||||
void mtk_ethdr_enable_vblank(struct device *dev);
|
||||
void mtk_ethdr_disable_vblank(struct device *dev);
|
||||
#endif
|
||||
Loading…
Reference in a new issue