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				https://github.com/torvalds/linux.git
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	platform-drivers-x86 for v6.13-3
Fixes and new HW support:
 
  - alienware-wmi: Add support for Alienware m16 R1 AMD.
 
  - alienware-wmi: Do not setup legacy LED control with X and G Series.
 
  - intel/ifs: Clearwater Forest support.
 
  - intel/vsec: Panther Lake support.
 
  - p2sb: Do not hide the device if BIOS left it unhidden.
 
  - touchscreen_dmi: Add SARY Tab 3 tablet information.
 
 The following is an automated shortlog grouped by driver:
 
 alienware-wmi:
  -  Adds support to Alienware m16 R1 AMD
  -  Fix X Series and G Series quirks
 
 intel/ifs:
  -  Add Clearwater Forest to CPU support list
 
 intel/vsec:
  -  Add support for Panther Lake
 
 p2sb:
  -  Do not scan and remove the P2SB device when it is unhidden
  -  Factor out p2sb_read_from_cache()
  -  Introduce the global flag p2sb_hidden_by_bios
  -  Move P2SB hide and unhide code to p2sb_scan_and_cache()
 
 touchscreen_dmi:
  -  Add info for SARY Tab 3 tablet
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Merge tag 'platform-drivers-x86-v6.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
Pull x86 platform driver fixes from Ilpo Järvinen:
 - alienware-wmi:
    - Add support for Alienware m16 R1 AMD
    - Do not setup legacy LED control with X and G Series
 - intel/ifs: Clearwater Forest support
 - intel/vsec: Panther Lake support
 - p2sb: Do not hide the device if BIOS left it unhidden
 - touchscreen_dmi: Add SARY Tab 3 tablet information
* tag 'platform-drivers-x86-v6.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86:
  platform/x86/intel/vsec: Add support for Panther Lake
  platform/x86/intel/ifs: Add Clearwater Forest to CPU support list
  platform/x86: touchscreen_dmi: Add info for SARY Tab 3 tablet
  p2sb: Do not scan and remove the P2SB device when it is unhidden
  p2sb: Move P2SB hide and unhide code to p2sb_scan_and_cache()
  p2sb: Introduce the global flag p2sb_hidden_by_bios
  p2sb: Factor out p2sb_read_from_cache()
  alienware-wmi: Adds support to Alienware m16 R1 AMD
  alienware-wmi: Fix X Series and G Series quirks
			
			
This commit is contained in:
		
						commit
						dc690bc256
					
				
					 5 changed files with 104 additions and 28 deletions
				
			
		| 
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			@ -190,7 +190,7 @@ static struct quirk_entry quirk_asm201 = {
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};
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static struct quirk_entry quirk_g_series = {
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	.num_zones = 2,
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	.num_zones = 0,
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	.hdmi_mux = 0,
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	.amplifier = 0,
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	.deepslp = 0,
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			@ -199,7 +199,7 @@ static struct quirk_entry quirk_g_series = {
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};
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static struct quirk_entry quirk_x_series = {
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	.num_zones = 2,
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	.num_zones = 0,
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	.hdmi_mux = 0,
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	.amplifier = 0,
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	.deepslp = 0,
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			@ -241,6 +241,15 @@ static const struct dmi_system_id alienware_quirks[] __initconst = {
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		},
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		.driver_data = &quirk_asm201,
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	},
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	{
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		.callback = dmi_matched,
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		.ident = "Alienware m16 R1 AMD",
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		.matches = {
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			DMI_MATCH(DMI_SYS_VENDOR, "Alienware"),
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			DMI_MATCH(DMI_PRODUCT_NAME, "Alienware m16 R1 AMD"),
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		},
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		.driver_data = &quirk_x_series,
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	},
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	{
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		.callback = dmi_matched,
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		.ident = "Alienware m17 R5",
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			@ -687,6 +696,9 @@ static void alienware_zone_exit(struct platform_device *dev)
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{
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	u8 zone;
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	if (!quirks->num_zones)
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		return;
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	sysfs_remove_group(&dev->dev.kobj, &zone_attribute_group);
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	led_classdev_unregister(&global_led);
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	if (zone_dev_attrs) {
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			@ -1229,9 +1241,11 @@ static int __init alienware_wmi_init(void)
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			goto fail_prep_thermal_profile;
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	}
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	ret = alienware_zone_init(platform_device);
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	if (ret)
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		goto fail_prep_zones;
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	if (quirks->num_zones > 0) {
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		ret = alienware_zone_init(platform_device);
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		if (ret)
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			goto fail_prep_zones;
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	}
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	return 0;
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			@ -20,6 +20,7 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
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	X86_MATCH(INTEL_GRANITERAPIDS_X, ARRAY_GEN0),
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	X86_MATCH(INTEL_GRANITERAPIDS_D, ARRAY_GEN0),
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	X86_MATCH(INTEL_ATOM_CRESTMONT_X, ARRAY_GEN1),
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	X86_MATCH(INTEL_ATOM_DARKMONT_X, ARRAY_GEN1),
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	{}
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};
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MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
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			@ -423,6 +423,7 @@ static const struct intel_vsec_platform_info lnl_info = {
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#define PCI_DEVICE_ID_INTEL_VSEC_RPL		0xa77d
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#define PCI_DEVICE_ID_INTEL_VSEC_TGL		0x9a0d
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#define PCI_DEVICE_ID_INTEL_VSEC_LNL_M		0x647d
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#define PCI_DEVICE_ID_INTEL_VSEC_PTL		0xb07d
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static const struct pci_device_id intel_vsec_pci_ids[] = {
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	{ PCI_DEVICE_DATA(INTEL, VSEC_ADL, &tgl_info) },
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	{ PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) },
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			@ -432,6 +433,7 @@ static const struct pci_device_id intel_vsec_pci_ids[] = {
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	{ PCI_DEVICE_DATA(INTEL, VSEC_RPL, &tgl_info) },
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	{ PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) },
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	{ PCI_DEVICE_DATA(INTEL, VSEC_LNL_M, &lnl_info) },
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	{ PCI_DEVICE_DATA(INTEL, VSEC_PTL, &mtl_info) },
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	{ }
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};
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MODULE_DEVICE_TABLE(pci, intel_vsec_pci_ids);
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			@ -43,6 +43,7 @@ struct p2sb_res_cache {
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};
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static struct p2sb_res_cache p2sb_resources[NR_P2SB_RES_CACHE];
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static bool p2sb_hidden_by_bios;
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static void p2sb_get_devfn(unsigned int *devfn)
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{
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			@ -97,6 +98,12 @@ static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn)
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static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn)
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{
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	/*
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	 * The BIOS prevents the P2SB device from being enumerated by the PCI
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	 * subsystem, so we need to unhide and hide it back to lookup the BAR.
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	 */
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	pci_bus_write_config_dword(bus, devfn, P2SBC, 0);
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	/* Scan the P2SB device and cache its BAR0 */
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	p2sb_scan_and_cache_devfn(bus, devfn);
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			@ -104,6 +111,8 @@ static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn)
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	if (devfn == P2SB_DEVFN_GOLDMONT)
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		p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT);
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	pci_bus_write_config_dword(bus, devfn, P2SBC, P2SBC_HIDE);
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	if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res))
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		return -ENOENT;
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			@ -129,7 +138,7 @@ static int p2sb_cache_resources(void)
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	u32 value = P2SBC_HIDE;
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	struct pci_bus *bus;
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	u16 class;
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	int ret;
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	int ret = 0;
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	/* Get devfn for P2SB device itself */
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	p2sb_get_devfn(&devfn_p2sb);
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			@ -152,26 +161,57 @@ static int p2sb_cache_resources(void)
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	 */
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	pci_lock_rescan_remove();
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	/*
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	 * The BIOS prevents the P2SB device from being enumerated by the PCI
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	 * subsystem, so we need to unhide and hide it back to lookup the BAR.
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	 * Unhide the P2SB device here, if needed.
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	 */
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	pci_bus_read_config_dword(bus, devfn_p2sb, P2SBC, &value);
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	if (value & P2SBC_HIDE)
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		pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, 0);
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	p2sb_hidden_by_bios = value & P2SBC_HIDE;
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	ret = p2sb_scan_and_cache(bus, devfn_p2sb);
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	/* Hide the P2SB device, if it was hidden */
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	if (value & P2SBC_HIDE)
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		pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, P2SBC_HIDE);
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	/*
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	 * If the BIOS does not hide the P2SB device then its resources
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	 * are accesilble. Cache them only if the P2SB device is hidden.
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	 */
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	if (p2sb_hidden_by_bios)
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		ret = p2sb_scan_and_cache(bus, devfn_p2sb);
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	pci_unlock_rescan_remove();
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	return ret;
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}
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static int p2sb_read_from_cache(struct pci_bus *bus, unsigned int devfn,
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				struct resource *mem)
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{
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	struct p2sb_res_cache *cache = &p2sb_resources[PCI_FUNC(devfn)];
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	if (cache->bus_dev_id != bus->dev.id)
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		return -ENODEV;
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	if (!p2sb_valid_resource(&cache->res))
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		return -ENOENT;
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	memcpy(mem, &cache->res, sizeof(*mem));
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	return 0;
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}
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static int p2sb_read_from_dev(struct pci_bus *bus, unsigned int devfn,
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			      struct resource *mem)
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{
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	struct pci_dev *pdev;
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	int ret = 0;
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	pdev = pci_get_slot(bus, devfn);
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	if (!pdev)
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		return -ENODEV;
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	if (p2sb_valid_resource(pci_resource_n(pdev, 0)))
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		p2sb_read_bar0(pdev, mem);
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	else
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		ret = -ENOENT;
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	pci_dev_put(pdev);
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	return ret;
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}
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/**
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 * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR
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 * @bus: PCI bus to communicate with
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			@ -188,8 +228,6 @@ static int p2sb_cache_resources(void)
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 */
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int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem)
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{
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	struct p2sb_res_cache *cache;
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	bus = p2sb_get_bus(bus);
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	if (!bus)
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		return -ENODEV;
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			@ -197,15 +235,10 @@ int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem)
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	if (!devfn)
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		p2sb_get_devfn(&devfn);
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	cache = &p2sb_resources[PCI_FUNC(devfn)];
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	if (cache->bus_dev_id != bus->dev.id)
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		return -ENODEV;
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	if (p2sb_hidden_by_bios)
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		return p2sb_read_from_cache(bus, devfn, mem);
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	if (!p2sb_valid_resource(&cache->res))
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		return -ENOENT;
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	memcpy(mem, &cache->res, sizeof(*mem));
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	return 0;
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	return p2sb_read_from_dev(bus, devfn, mem);
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}
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EXPORT_SYMBOL_GPL(p2sb_bar);
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			@ -855,6 +855,23 @@ static const struct ts_dmi_data rwc_nanote_next_data = {
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	.properties = rwc_nanote_next_props,
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};
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static const struct property_entry sary_tab_3_props[] = {
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	PROPERTY_ENTRY_U32("touchscreen-size-x", 1730),
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	PROPERTY_ENTRY_U32("touchscreen-size-y", 1151),
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	PROPERTY_ENTRY_BOOL("touchscreen-inverted-x"),
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	PROPERTY_ENTRY_BOOL("touchscreen-inverted-y"),
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	PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"),
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	PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-sary-tab-3.fw"),
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	PROPERTY_ENTRY_U32("silead,max-fingers", 10),
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	PROPERTY_ENTRY_BOOL("silead,home-button"),
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	{ }
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};
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static const struct ts_dmi_data sary_tab_3_data = {
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	.acpi_name	= "MSSL1680:00",
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	.properties	= sary_tab_3_props,
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};
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static const struct property_entry schneider_sct101ctm_props[] = {
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	PROPERTY_ENTRY_U32("touchscreen-size-x", 1715),
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	PROPERTY_ENTRY_U32("touchscreen-size-y", 1140),
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| 
						 | 
				
			
			@ -1615,6 +1632,15 @@ const struct dmi_system_id touchscreen_dmi_table[] = {
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			DMI_MATCH(DMI_BIOS_VERSION, "S8A70R100-V005"),
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		},
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	},
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	{
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		/* SARY Tab 3 */
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		.driver_data = (void *)&sary_tab_3_data,
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		.matches = {
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			DMI_MATCH(DMI_SYS_VENDOR, "SARY"),
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			DMI_MATCH(DMI_PRODUCT_NAME, "C210C"),
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			DMI_MATCH(DMI_PRODUCT_SKU, "TAB3"),
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		},
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	},
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	{
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		/* Schneider SCT101CTM */
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		.driver_data = (void *)&schneider_sct101ctm_data,
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| 
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