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	ARM: clk-imx6q: Add CAAM clock support
Add CAAM clock support to the i.MX6 clocking infrastructure. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> Tested-by: Horia Geantă <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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					 2 changed files with 7 additions and 1 deletions
				
			
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					@ -381,6 +381,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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	clk[IMX6QDL_CLK_ASRC]         = imx_clk_gate2_shared("asrc",         "asrc_podf",   base + 0x68, 6, &share_count_asrc);
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						clk[IMX6QDL_CLK_ASRC]         = imx_clk_gate2_shared("asrc",         "asrc_podf",   base + 0x68, 6, &share_count_asrc);
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	clk[IMX6QDL_CLK_ASRC_IPG]     = imx_clk_gate2_shared("asrc_ipg",     "ahb",         base + 0x68, 6, &share_count_asrc);
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						clk[IMX6QDL_CLK_ASRC_IPG]     = imx_clk_gate2_shared("asrc_ipg",     "ahb",         base + 0x68, 6, &share_count_asrc);
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	clk[IMX6QDL_CLK_ASRC_MEM]     = imx_clk_gate2_shared("asrc_mem",     "ahb",         base + 0x68, 6, &share_count_asrc);
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						clk[IMX6QDL_CLK_ASRC_MEM]     = imx_clk_gate2_shared("asrc_mem",     "ahb",         base + 0x68, 6, &share_count_asrc);
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						clk[IMX6QDL_CLK_CAAM_MEM]     = imx_clk_gate2("caam_mem",      "ahb",               base + 0x68, 8);
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						clk[IMX6QDL_CLK_CAAM_ACLK]    = imx_clk_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
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						clk[IMX6QDL_CLK_CAAM_IPG]     = imx_clk_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
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	clk[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
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						clk[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
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	clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
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						clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
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	clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
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						clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
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					@ -251,6 +251,9 @@
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#define IMX6QDL_CLK_VIDEO_27M			238
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					#define IMX6QDL_CLK_VIDEO_27M			238
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#define IMX6QDL_CLK_MIPI_CORE_CFG		239
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					#define IMX6QDL_CLK_MIPI_CORE_CFG		239
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#define IMX6QDL_CLK_MIPI_IPG			240
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					#define IMX6QDL_CLK_MIPI_IPG			240
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#define IMX6QDL_CLK_END				241
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					#define IMX6QDL_CLK_CAAM_MEM			241
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					#define IMX6QDL_CLK_CAAM_ACLK			242
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					#define IMX6QDL_CLK_CAAM_IPG			243
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					#define IMX6QDL_CLK_END				244
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#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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					#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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