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pinctrl: intel: Add Intel Jasper Lake pin controller support
This driver adds pinctrl/GPIO support for Intel Jasper Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Andy Shevchenko
parent
9bd59157e1
commit
e278dcb704
3 changed files with 353 additions and 0 deletions
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@ -111,6 +111,14 @@ config PINCTRL_ICELAKE
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This pinctrl driver provides an interface that allows configuring
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of Intel Ice Lake PCH pins and using them as GPIOs.
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config PINCTRL_JASPERLAKE
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tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"
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depends on ACPI
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select PINCTRL_INTEL
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help
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This pinctrl driver provides an interface that allows configuring
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of Intel Jasper Lake PCH pins and using them as GPIOs.
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config PINCTRL_LEWISBURG
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tristate "Intel Lewisburg pinctrl and GPIO driver"
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depends on ACPI
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@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o
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obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
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obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
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obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
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obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o
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obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
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obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
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obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o
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344
drivers/pinctrl/intel/pinctrl-jasperlake.c
Normal file
344
drivers/pinctrl/intel/pinctrl-jasperlake.c
Normal file
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@ -0,0 +1,344 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Jasper Lake PCH pinctrl/GPIO driver
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*
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* Copyright (C) 2020, Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*/
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-intel.h"
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#define JSL_PAD_OWN 0x020
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#define JSL_PADCFGLOCK 0x080
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#define JSL_HOSTSW_OWN 0x0b0
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#define JSL_GPI_IS 0x100
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#define JSL_GPI_IE 0x120
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#define JSL_GPP(r, s, e, g) \
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{ \
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.reg_num = (r), \
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.base = (s), \
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.size = ((e) - (s) + 1), \
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.gpio_base = (g), \
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}
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#define JSL_COMMUNITY(b, s, e, g) \
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{ \
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.barno = (b), \
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.padown_offset = JSL_PAD_OWN, \
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.padcfglock_offset = JSL_PADCFGLOCK, \
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.hostown_offset = JSL_HOSTSW_OWN, \
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.is_offset = JSL_GPI_IS, \
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.ie_offset = JSL_GPI_IE, \
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.pin_base = (s), \
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.npins = ((e) - (s) + 1), \
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.gpps = (g), \
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.ngpps = ARRAY_SIZE(g), \
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}
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/* Jasper Lake */
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static const struct pinctrl_pin_desc jsl_pins[] = {
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/* GPP_F */
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PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"),
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PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"),
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PINCTRL_PIN(2, "EMMC_HIP_MON"),
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PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"),
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PINCTRL_PIN(4, "CNV_RF_RESET_B"),
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PINCTRL_PIN(5, "MODEM_CLKREQ"),
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PINCTRL_PIN(6, "CNV_PA_BLANKING"),
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PINCTRL_PIN(7, "EMMC_CMD"),
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PINCTRL_PIN(8, "EMMC_DATA0"),
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PINCTRL_PIN(9, "EMMC_DATA1"),
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PINCTRL_PIN(10, "EMMC_DATA2"),
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PINCTRL_PIN(11, "EMMC_DATA3"),
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PINCTRL_PIN(12, "EMMC_DATA4"),
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PINCTRL_PIN(13, "EMMC_DATA5"),
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PINCTRL_PIN(14, "EMMC_DATA6"),
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PINCTRL_PIN(15, "EMMC_DATA7"),
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PINCTRL_PIN(16, "EMMC_RCLK"),
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PINCTRL_PIN(17, "EMMC_CLK"),
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PINCTRL_PIN(18, "EMMC_RESETB"),
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PINCTRL_PIN(19, "A4WP_PRESENT"),
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/* GPP_B */
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PINCTRL_PIN(20, "CORE_VID_0"),
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PINCTRL_PIN(21, "CORE_VID_1"),
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PINCTRL_PIN(22, "VRALERTB"),
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PINCTRL_PIN(23, "CPU_GP_2"),
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PINCTRL_PIN(24, "CPU_GP_3"),
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PINCTRL_PIN(25, "SRCCLKREQB_0"),
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PINCTRL_PIN(26, "SRCCLKREQB_1"),
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PINCTRL_PIN(27, "SRCCLKREQB_2"),
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PINCTRL_PIN(28, "SRCCLKREQB_3"),
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PINCTRL_PIN(29, "SRCCLKREQB_4"),
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PINCTRL_PIN(30, "SRCCLKREQB_5"),
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PINCTRL_PIN(31, "PMCALERTB"),
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PINCTRL_PIN(32, "SLP_S0B"),
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PINCTRL_PIN(33, "PLTRSTB"),
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PINCTRL_PIN(34, "SPKR"),
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PINCTRL_PIN(35, "GSPI0_CS0B"),
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PINCTRL_PIN(36, "GSPI0_CLK"),
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PINCTRL_PIN(37, "GSPI0_MISO"),
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PINCTRL_PIN(38, "GSPI0_MOSI"),
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PINCTRL_PIN(39, "GSPI1_CS0B"),
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PINCTRL_PIN(40, "GSPI1_CLK"),
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PINCTRL_PIN(41, "GSPI1_MISO"),
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PINCTRL_PIN(42, "GSPI1_MOSI"),
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PINCTRL_PIN(43, "DDSP_HPD_A"),
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PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"),
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PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"),
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/* GPP_A */
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PINCTRL_PIN(46, "ESPI_IO_0"),
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PINCTRL_PIN(47, "ESPI_IO_1"),
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PINCTRL_PIN(48, "ESPI_IO_2"),
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PINCTRL_PIN(49, "ESPI_IO_3"),
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PINCTRL_PIN(50, "ESPI_CSB"),
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PINCTRL_PIN(51, "ESPI_CLK"),
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PINCTRL_PIN(52, "ESPI_RESETB"),
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PINCTRL_PIN(53, "SMBCLK"),
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PINCTRL_PIN(54, "SMBDATA"),
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PINCTRL_PIN(55, "SMBALERTB"),
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PINCTRL_PIN(56, "CPU_GP_0"),
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PINCTRL_PIN(57, "CPU_GP_1"),
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PINCTRL_PIN(58, "USB2_OCB_1"),
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PINCTRL_PIN(59, "USB2_OCB_2"),
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PINCTRL_PIN(60, "USB2_OCB_3"),
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PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"),
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PINCTRL_PIN(62, "DDSP_HPD_B"),
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PINCTRL_PIN(63, "DDSP_HPD_C"),
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PINCTRL_PIN(64, "USB2_OCB_0"),
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PINCTRL_PIN(65, "PCHHOTB"),
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PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
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/* GPP_S */
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PINCTRL_PIN(67, "SNDW1_CLK"),
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PINCTRL_PIN(68, "SNDW1_DATA"),
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PINCTRL_PIN(69, "SNDW2_CLK"),
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PINCTRL_PIN(70, "SNDW2_DATA"),
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PINCTRL_PIN(71, "SNDW1_CLK"),
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PINCTRL_PIN(72, "SNDW1_DATA"),
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PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"),
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PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"),
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/* GPP_R */
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PINCTRL_PIN(75, "HDA_BCLK"),
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PINCTRL_PIN(76, "HDA_SYNC"),
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PINCTRL_PIN(77, "HDA_SDO"),
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PINCTRL_PIN(78, "HDA_SDI_0"),
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PINCTRL_PIN(79, "HDA_RSTB"),
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PINCTRL_PIN(80, "HDA_SDI_1"),
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PINCTRL_PIN(81, "I2S1_SFRM"),
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PINCTRL_PIN(82, "I2S1_TXD"),
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/* GPP_H */
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PINCTRL_PIN(83, "GPPC_H_0"),
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PINCTRL_PIN(84, "SD_PWR_EN_B"),
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PINCTRL_PIN(85, "MODEM_CLKREQ"),
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PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"),
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PINCTRL_PIN(87, "I2C2_SDA"),
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PINCTRL_PIN(88, "I2C2_SCL"),
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PINCTRL_PIN(89, "I2C3_SDA"),
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PINCTRL_PIN(90, "I2C3_SCL"),
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PINCTRL_PIN(91, "I2C4_SDA"),
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PINCTRL_PIN(92, "I2C4_SCL"),
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PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"),
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PINCTRL_PIN(94, "I2S2_SCLK"),
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PINCTRL_PIN(95, "I2S2_SFRM"),
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PINCTRL_PIN(96, "I2S2_TXD"),
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PINCTRL_PIN(97, "I2S2_RXD"),
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PINCTRL_PIN(98, "I2S1_SCLK"),
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PINCTRL_PIN(99, "GPPC_H_16"),
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PINCTRL_PIN(100, "GPPC_H_17"),
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PINCTRL_PIN(101, "GPPC_H_18"),
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PINCTRL_PIN(102, "GPPC_H_19"),
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PINCTRL_PIN(103, "GPPC_H_20"),
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PINCTRL_PIN(104, "GPPC_H_21"),
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PINCTRL_PIN(105, "GPPC_H_22"),
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PINCTRL_PIN(106, "GPPC_H_23"),
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/* GPP_D */
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PINCTRL_PIN(107, "SPI1_CSB"),
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PINCTRL_PIN(108, "SPI1_CLK"),
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PINCTRL_PIN(109, "SPI1_MISO_IO_1"),
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PINCTRL_PIN(110, "SPI1_MOSI_IO_0"),
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PINCTRL_PIN(111, "ISH_I2C0_SDA"),
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PINCTRL_PIN(112, "ISH_I2C0_SCL"),
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PINCTRL_PIN(113, "ISH_I2C1_SDA"),
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PINCTRL_PIN(114, "ISH_I2C1_SCL"),
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PINCTRL_PIN(115, "ISH_SPI_CSB"),
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PINCTRL_PIN(116, "ISH_SPI_CLK"),
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PINCTRL_PIN(117, "ISH_SPI_MISO"),
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PINCTRL_PIN(118, "ISH_SPI_MOSI"),
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PINCTRL_PIN(119, "ISH_UART0_RXD"),
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PINCTRL_PIN(120, "ISH_UART0_TXD"),
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PINCTRL_PIN(121, "ISH_UART0_RTSB"),
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PINCTRL_PIN(122, "ISH_UART0_CTSB"),
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PINCTRL_PIN(123, "SPI1_IO_2"),
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PINCTRL_PIN(124, "SPI1_IO_3"),
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PINCTRL_PIN(125, "I2S_MCLK"),
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PINCTRL_PIN(126, "CNV_MFUART2_RXD"),
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PINCTRL_PIN(127, "CNV_MFUART2_TXD"),
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PINCTRL_PIN(128, "CNV_PA_BLANKING"),
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PINCTRL_PIN(129, "I2C5_SDA"),
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PINCTRL_PIN(130, "I2C5_SCL"),
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PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"),
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PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"),
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/* vGPIO */
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PINCTRL_PIN(133, "CNV_BTEN"),
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PINCTRL_PIN(134, "CNV_WCEN"),
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PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"),
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PINCTRL_PIN(136, "CNV_BT_IF_SELECT"),
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PINCTRL_PIN(137, "vCNV_BT_UART_TXD"),
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PINCTRL_PIN(138, "vCNV_BT_UART_RXD"),
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PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"),
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PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"),
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PINCTRL_PIN(141, "vCNV_MFUART1_TXD"),
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PINCTRL_PIN(142, "vCNV_MFUART1_RXD"),
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PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"),
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PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"),
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PINCTRL_PIN(145, "vUART0_TXD"),
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PINCTRL_PIN(146, "vUART0_RXD"),
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PINCTRL_PIN(147, "vUART0_CTS_B"),
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PINCTRL_PIN(148, "vUART0_RTS_B"),
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PINCTRL_PIN(149, "vISH_UART0_TXD"),
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PINCTRL_PIN(150, "vISH_UART0_RXD"),
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PINCTRL_PIN(151, "vISH_UART0_CTS_B"),
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PINCTRL_PIN(152, "vISH_UART0_RTS_B"),
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PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"),
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PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"),
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PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"),
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PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"),
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PINCTRL_PIN(157, "vI2S2_SCLK"),
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PINCTRL_PIN(158, "vI2S2_SFRM"),
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PINCTRL_PIN(159, "vI2S2_TXD"),
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PINCTRL_PIN(160, "vI2S2_RXD"),
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PINCTRL_PIN(161, "vSD3_CD_B"),
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/* GPP_C */
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PINCTRL_PIN(162, "GPPC_C_0"),
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PINCTRL_PIN(163, "GPPC_C_1"),
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PINCTRL_PIN(164, "GPPC_C_2"),
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PINCTRL_PIN(165, "GPPC_C_3"),
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PINCTRL_PIN(166, "GPPC_C_4"),
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PINCTRL_PIN(167, "GPPC_C_5"),
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PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"),
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PINCTRL_PIN(169, "SUSACKB"),
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PINCTRL_PIN(170, "UART0_RXD"),
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PINCTRL_PIN(171, "UART0_TXD"),
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PINCTRL_PIN(172, "UART0_RTSB"),
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PINCTRL_PIN(173, "UART0_CTSB"),
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PINCTRL_PIN(174, "UART1_RXD"),
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PINCTRL_PIN(175, "UART1_TXD"),
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PINCTRL_PIN(176, "UART1_RTSB"),
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PINCTRL_PIN(177, "UART1_CTSB"),
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PINCTRL_PIN(178, "I2C0_SDA"),
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PINCTRL_PIN(179, "I2C0_SCL"),
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PINCTRL_PIN(180, "I2C1_SDA"),
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PINCTRL_PIN(181, "I2C1_SCL"),
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PINCTRL_PIN(182, "UART2_RXD"),
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PINCTRL_PIN(183, "UART2_TXD"),
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PINCTRL_PIN(184, "UART2_RTSB"),
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PINCTRL_PIN(185, "UART2_CTSB"),
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/* HVCMOS */
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PINCTRL_PIN(186, "L_BKLTEN"),
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PINCTRL_PIN(187, "L_BKLTCTL"),
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PINCTRL_PIN(188, "L_VDDEN"),
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PINCTRL_PIN(189, "SYS_PWROK"),
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PINCTRL_PIN(190, "SYS_RESETB"),
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PINCTRL_PIN(191, "MLK_RSTB"),
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/* GPP_E */
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PINCTRL_PIN(192, "ISH_GP_0"),
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PINCTRL_PIN(193, "ISH_GP_1"),
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PINCTRL_PIN(194, "IMGCLKOUT_1"),
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PINCTRL_PIN(195, "ISH_GP_2"),
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PINCTRL_PIN(196, "IMGCLKOUT_2"),
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PINCTRL_PIN(197, "SATA_LEDB"),
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PINCTRL_PIN(198, "IMGCLKOUT_3"),
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PINCTRL_PIN(199, "ISH_GP_3"),
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PINCTRL_PIN(200, "ISH_GP_4"),
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PINCTRL_PIN(201, "ISH_GP_5"),
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PINCTRL_PIN(202, "ISH_GP_6"),
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PINCTRL_PIN(203, "ISH_GP_7"),
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PINCTRL_PIN(204, "IMGCLKOUT_4"),
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PINCTRL_PIN(205, "DDPA_CTRLCLK"),
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PINCTRL_PIN(206, "DDPA_CTRLDATA"),
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PINCTRL_PIN(207, "DDPB_CTRLCLK"),
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PINCTRL_PIN(208, "DDPB_CTRLDATA"),
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PINCTRL_PIN(209, "DDPC_CTRLCLK"),
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PINCTRL_PIN(210, "DDPC_CTRLDATA"),
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PINCTRL_PIN(211, "IMGCLKOUT_5"),
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PINCTRL_PIN(212, "CNV_BRI_DT"),
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PINCTRL_PIN(213, "CNV_BRI_RSP"),
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PINCTRL_PIN(214, "CNV_RGI_DT"),
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PINCTRL_PIN(215, "CNV_RGI_RSP"),
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/* GPP_G */
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PINCTRL_PIN(216, "SD3_CMD"),
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PINCTRL_PIN(217, "SD3_D0"),
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PINCTRL_PIN(218, "SD3_D1"),
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PINCTRL_PIN(219, "SD3_D2"),
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PINCTRL_PIN(220, "SD3_D3"),
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PINCTRL_PIN(221, "SD3_CDB"),
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PINCTRL_PIN(222, "SD3_CLK"),
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PINCTRL_PIN(223, "SD3_WP"),
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};
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static const struct intel_padgroup jsl_community0_gpps[] = {
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JSL_GPP(0, 0, 19, 320), /* GPP_F */
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JSL_GPP(1, 20, 45, 32), /* GPP_B */
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JSL_GPP(2, 46, 66, 64), /* GPP_A */
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JSL_GPP(3, 67, 74, 96), /* GPP_S */
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JSL_GPP(4, 75, 82, 128), /* GPP_R */
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};
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static const struct intel_padgroup jsl_community1_gpps[] = {
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JSL_GPP(0, 83, 106, 160), /* GPP_H */
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JSL_GPP(1, 107, 132, 192), /* GPP_D */
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JSL_GPP(2, 133, 161, 224), /* vGPIO */
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JSL_GPP(3, 162, 185, 256), /* GPP_C */
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};
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static const struct intel_padgroup jsl_community4_gpps[] = {
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JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
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JSL_GPP(1, 192, 215, 288), /* GPP_E */
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};
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static const struct intel_padgroup jsl_community5_gpps[] = {
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JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */
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};
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static const struct intel_community jsl_communities[] = {
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JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps),
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JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps),
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JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps),
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JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps),
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};
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static const struct intel_pinctrl_soc_data jsl_soc_data = {
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.pins = jsl_pins,
|
||||
.npins = ARRAY_SIZE(jsl_pins),
|
||||
.communities = jsl_communities,
|
||||
.ncommunities = ARRAY_SIZE(jsl_communities),
|
||||
};
|
||||
|
||||
static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {
|
||||
{ "INT34C8", (kernel_ulong_t)&jsl_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
|
||||
|
||||
static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops);
|
||||
|
||||
static struct platform_driver jsl_pinctrl_driver = {
|
||||
.probe = intel_pinctrl_probe_by_hid,
|
||||
.driver = {
|
||||
.name = "jasperlake-pinctrl",
|
||||
.acpi_match_table = jsl_pinctrl_acpi_match,
|
||||
.pm = &jsl_pinctrl_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(jsl_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
||||
MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue