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arm: orion: Use generic irq chip
The core interrupt chip is a straight forward conversion. The gpio chip is implemented with two instances of the irq_chip_type which can be switched with the irq_set_type function. That allows us to use the generic callbacks and avoids the conditionals in them. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
This commit is contained in:
Thomas Gleixner
Nicolas Pitre
parent
cfefd21e69
commit
e59347a1d1
3 changed files with 44 additions and 116 deletions
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@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
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* polarity LEVEL mask
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*
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****************************************************************************/
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static void gpio_irq_ack(struct irq_data *d)
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{
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struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
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int type = irqd_get_trigger_type(d);
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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int pin = d->irq - ochip->secondary_irq_base;
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writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
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}
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}
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static void gpio_irq_mask(struct irq_data *d)
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{
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struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
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int type = irqd_get_trigger_type(d);
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void __iomem *reg;
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int pin;
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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reg = GPIO_EDGE_MASK(ochip);
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else
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reg = GPIO_LEVEL_MASK(ochip);
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pin = d->irq - ochip->secondary_irq_base;
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writel(readl(reg) & ~(1 << pin), reg);
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}
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static void gpio_irq_unmask(struct irq_data *d)
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{
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struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
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int type = irqd_get_trigger_type(d);
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void __iomem *reg;
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int pin;
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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reg = GPIO_EDGE_MASK(ochip);
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else
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reg = GPIO_LEVEL_MASK(ochip);
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pin = d->irq - ochip->secondary_irq_base;
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writel(readl(reg) | (1 << pin), reg);
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}
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static int gpio_irq_set_type(struct irq_data *d, u32 type)
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{
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struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct orion_gpio_chip *ochip = gc->private;
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int pin;
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u32 u;
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pin = d->irq - ochip->secondary_irq_base;
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pin = d->irq - gc->irq_base;
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u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
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if (!u) {
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@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
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return -EINVAL;
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}
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/*
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* Set edge/level type.
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*/
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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__irq_set_handler_locked(d->irq, handle_level_irq);
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} else {
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printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
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d->irq, type);
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type &= IRQ_TYPE_SENSE_MASK;
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if (type == IRQ_TYPE_NONE)
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return -EINVAL;
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}
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/* Check if we need to change chip and handler */
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if (!(ct->type & type))
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if (irq_setup_alt_chip(d, type))
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return -EINVAL;
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/*
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* Configure interrupt polarity.
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@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
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return 0;
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}
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struct irq_chip orion_gpio_irq_chip = {
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.name = "orion_gpio_irq",
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.irq_ack = gpio_irq_ack,
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.irq_mask = gpio_irq_mask,
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.irq_unmask = gpio_irq_unmask,
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.irq_set_type = gpio_irq_set_type,
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};
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void __init orion_gpio_init(int gpio_base, int ngpio,
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u32 base, int mask_offset, int secondary_irq_base)
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{
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struct orion_gpio_chip *ochip;
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int i;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
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return;
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@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
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writel(0, GPIO_EDGE_MASK(ochip));
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writel(0, GPIO_LEVEL_MASK(ochip));
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for (i = 0; i < ngpio; i++) {
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unsigned int irq = secondary_irq_base + i;
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gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
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ochip->base, handle_level_irq);
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gc->private = ochip;
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irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, ochip);
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irq_set_status_flags(irq, IRQ_LEVEL);
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set_irq_flags(irq, IRQF_VALID);
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}
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ct = gc->chip_types;
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ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_irq_set_type;
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ct++;
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ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
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ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
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ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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ct->chip.irq_ack = irq_gc_ack;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_irq_set_type;
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ct->handler = handle_edge_irq;
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irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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}
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void orion_gpio_irq_handler(int pinoff)
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@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
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/*
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* GPIO interrupt handling.
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*/
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extern struct irq_chip orion_gpio_irq_chip;
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void orion_gpio_irq_handler(int irqoff);
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@ -14,52 +14,21 @@
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#include <linux/io.h>
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#include <plat/irq.h>
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static void orion_irq_mask(struct irq_data *d)
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{
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void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
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u32 mask;
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mask = readl(maskaddr);
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mask &= ~(1 << (d->irq & 31));
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writel(mask, maskaddr);
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}
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static void orion_irq_unmask(struct irq_data *d)
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{
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void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
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u32 mask;
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mask = readl(maskaddr);
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mask |= 1 << (d->irq & 31);
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writel(mask, maskaddr);
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}
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static struct irq_chip orion_irq_chip = {
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.name = "orion_irq",
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.irq_mask = orion_irq_mask,
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.irq_mask_ack = orion_irq_mask,
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.irq_unmask = orion_irq_unmask,
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};
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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unsigned int i;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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/*
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* Mask all interrupts initially.
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*/
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writel(0, maskaddr);
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/*
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* Register IRQ sources.
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*/
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for (i = 0; i < 32; i++) {
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unsigned int irq = irq_start + i;
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irq_set_chip_and_handler(irq, &orion_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, maskaddr);
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irq_set_status_flags(irq, IRQ_LEVEL);
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set_irq_flags(irq, IRQF_VALID);
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}
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gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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}
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