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genirq/msi: Switch to new irq spreading infrastructure
Switch MSI over to the new spreading code. If a pci device contains a valid pointer to a cpumask, then this mask is used for spreading otherwise the online cpu mask is used. This allows a driver to restrict the spread to a subset of CPUs, e.g. cpus on a particular node. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Christoph Hellwig <hch@lst.de> Cc: axboe@fb.com Cc: keith.busch@intel.com Cc: agordeev@redhat.com Cc: linux-block@vger.kernel.org Link: http://lkml.kernel.org/r/1473862739-15032-4-git-send-email-hch@lst.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner
parent
34c3d9819f
commit
e75eafb9b0
2 changed files with 86 additions and 71 deletions
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@ -549,15 +549,23 @@ static int populate_msi_sysfs(struct pci_dev *pdev)
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return ret;
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}
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static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
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static struct msi_desc *
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msi_setup_entry(struct pci_dev *dev, int nvec, bool affinity)
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{
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u16 control;
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struct cpumask *masks = NULL;
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struct msi_desc *entry;
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u16 control;
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if (affinity) {
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masks = irq_create_affinity_masks(dev->irq_affinity, nvec);
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if (!masks)
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pr_err("Unable to allocate affinity masks, ignoring\n");
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}
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/* MSI Entry Initialization */
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entry = alloc_msi_entry(&dev->dev, nvec, NULL);
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entry = alloc_msi_entry(&dev->dev, nvec, masks);
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if (!entry)
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return NULL;
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goto out;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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@ -568,7 +576,6 @@ static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
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entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
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entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
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entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
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entry->affinity = dev->irq_affinity;
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if (control & PCI_MSI_FLAGS_64BIT)
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entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
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@ -579,6 +586,8 @@ static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
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if (entry->msi_attrib.maskbit)
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pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
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out:
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kfree(masks);
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return entry;
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}
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@ -607,7 +616,7 @@ static int msi_verify_entries(struct pci_dev *dev)
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* an error, and a positive return value indicates the number of interrupts
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* which could have been allocated.
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*/
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static int msi_capability_init(struct pci_dev *dev, int nvec)
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static int msi_capability_init(struct pci_dev *dev, int nvec, bool affinity)
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{
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struct msi_desc *entry;
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int ret;
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@ -615,7 +624,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
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pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
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entry = msi_setup_entry(dev, nvec);
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entry = msi_setup_entry(dev, nvec, affinity);
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if (!entry)
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return -ENOMEM;
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@ -678,28 +687,29 @@ static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
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}
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static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
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struct msix_entry *entries, int nvec)
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struct msix_entry *entries, int nvec,
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bool affinity)
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{
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const struct cpumask *mask = NULL;
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struct cpumask *curmsk, *masks = NULL;
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struct msi_desc *entry;
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int cpu = -1, i;
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int ret, i;
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for (i = 0; i < nvec; i++) {
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if (dev->irq_affinity) {
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cpu = cpumask_next(cpu, dev->irq_affinity);
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if (cpu >= nr_cpu_ids)
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cpu = cpumask_first(dev->irq_affinity);
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mask = cpumask_of(cpu);
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}
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if (affinity) {
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masks = irq_create_affinity_masks(dev->irq_affinity, nvec);
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if (!masks)
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pr_err("Unable to allocate affinity masks, ignoring\n");
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}
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entry = alloc_msi_entry(&dev->dev, 1, NULL);
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for (i = 0, curmsk = masks; i < nvec; i++) {
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entry = alloc_msi_entry(&dev->dev, 1, curmsk);
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if (!entry) {
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if (!i)
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iounmap(base);
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else
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free_msi_irqs(dev);
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/* No enough memory. Don't try again */
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return -ENOMEM;
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ret = -ENOMEM;
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goto out;
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}
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entry->msi_attrib.is_msix = 1;
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@ -710,11 +720,14 @@ static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
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entry->msi_attrib.entry_nr = i;
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entry->msi_attrib.default_irq = dev->irq;
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entry->mask_base = base;
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entry->affinity = mask;
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list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
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if (masks)
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curmsk++;
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}
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ret = 0;
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out:
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kfree(masks);
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return 0;
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}
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@ -743,8 +756,8 @@ static void msix_program_entries(struct pci_dev *dev,
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* single MSI-X irq. A return of zero indicates the successful setup of
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* requested MSI-X entries with allocated irqs or non-zero for otherwise.
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**/
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static int msix_capability_init(struct pci_dev *dev,
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struct msix_entry *entries, int nvec)
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static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
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int nvec, bool affinity)
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{
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int ret;
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u16 control;
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@ -759,7 +772,7 @@ static int msix_capability_init(struct pci_dev *dev,
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if (!base)
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return -ENOMEM;
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ret = msix_setup_entries(dev, base, entries, nvec);
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ret = msix_setup_entries(dev, base, entries, nvec, affinity);
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if (ret)
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return ret;
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@ -939,22 +952,8 @@ int pci_msix_vec_count(struct pci_dev *dev)
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}
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EXPORT_SYMBOL(pci_msix_vec_count);
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/**
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* pci_enable_msix - configure device's MSI-X capability structure
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* @dev: pointer to the pci_dev data structure of MSI-X device function
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* @entries: pointer to an array of MSI-X entries (optional)
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* @nvec: number of MSI-X irqs requested for allocation by device driver
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*
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* Setup the MSI-X capability structure of device function with the number
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* of requested irqs upon its software driver call to request for
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* MSI-X mode enabled on its hardware device function. A return of zero
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* indicates the successful configuration of MSI-X capability structure
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* with new allocated MSI-X irqs. A return of < 0 indicates a failure.
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* Or a return of > 0 indicates that driver request is exceeding the number
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* of irqs or MSI-X vectors available. Driver should use the returned value to
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* re-send its request.
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**/
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int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
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static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
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int nvec, bool affinity)
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{
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int nr_entries;
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int i, j;
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@ -986,7 +985,27 @@ int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
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dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
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return -EINVAL;
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}
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return msix_capability_init(dev, entries, nvec);
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return msix_capability_init(dev, entries, nvec, affinity);
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}
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/**
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* pci_enable_msix - configure device's MSI-X capability structure
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* @dev: pointer to the pci_dev data structure of MSI-X device function
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* @entries: pointer to an array of MSI-X entries (optional)
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* @nvec: number of MSI-X irqs requested for allocation by device driver
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*
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* Setup the MSI-X capability structure of device function with the number
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* of requested irqs upon its software driver call to request for
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* MSI-X mode enabled on its hardware device function. A return of zero
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* indicates the successful configuration of MSI-X capability structure
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* with new allocated MSI-X irqs. A return of < 0 indicates a failure.
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* Or a return of > 0 indicates that driver request is exceeding the number
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* of irqs or MSI-X vectors available. Driver should use the returned value to
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* re-send its request.
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**/
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int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
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{
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return __pci_enable_msix(dev, entries, nvec, false);
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}
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EXPORT_SYMBOL(pci_enable_msix);
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@ -1039,6 +1058,7 @@ EXPORT_SYMBOL(pci_msi_enabled);
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static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
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unsigned int flags)
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{
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bool affinity = flags & PCI_IRQ_AFFINITY;
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int nvec;
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int rc;
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@ -1067,19 +1087,17 @@ static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
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nvec = maxvec;
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for (;;) {
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if (flags & PCI_IRQ_AFFINITY) {
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dev->irq_affinity = irq_create_affinity_mask(&nvec);
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if (affinity) {
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nvec = irq_calc_affinity_vectors(dev->irq_affinity,
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nvec);
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if (nvec < minvec)
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return -ENOSPC;
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}
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rc = msi_capability_init(dev, nvec);
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rc = msi_capability_init(dev, nvec, affinity);
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if (rc == 0)
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return nvec;
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kfree(dev->irq_affinity);
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dev->irq_affinity = NULL;
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if (rc < 0)
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return rc;
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if (rc < minvec)
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@ -1111,26 +1129,24 @@ static int __pci_enable_msix_range(struct pci_dev *dev,
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struct msix_entry *entries, int minvec, int maxvec,
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unsigned int flags)
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{
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int nvec = maxvec;
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int rc;
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bool affinity = flags & PCI_IRQ_AFFINITY;
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int rc, nvec = maxvec;
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if (maxvec < minvec)
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return -ERANGE;
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for (;;) {
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if (flags & PCI_IRQ_AFFINITY) {
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dev->irq_affinity = irq_create_affinity_mask(&nvec);
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if (affinity) {
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nvec = irq_calc_affinity_vectors(dev->irq_affinity,
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nvec);
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if (nvec < minvec)
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return -ENOSPC;
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}
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rc = pci_enable_msix(dev, entries, nvec);
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rc = __pci_enable_msix(dev, entries, nvec, affinity);
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if (rc == 0)
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return nvec;
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kfree(dev->irq_affinity);
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dev->irq_affinity = NULL;
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if (rc < 0)
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return rc;
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if (rc < minvec)
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@ -236,25 +236,24 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node,
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const struct cpumask *mask = NULL;
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struct irq_desc *desc;
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unsigned int flags;
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int i, cpu = -1;
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int i;
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if (affinity && cpumask_empty(affinity))
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return -EINVAL;
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/* Validate affinity mask(s) */
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if (affinity) {
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for (i = 0, mask = affinity; i < cnt; i++, mask++) {
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if (cpumask_empty(mask))
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return -EINVAL;
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}
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}
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flags = affinity ? IRQD_AFFINITY_MANAGED : 0;
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mask = NULL;
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for (i = 0; i < cnt; i++) {
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if (affinity) {
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cpu = cpumask_next(cpu, affinity);
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if (cpu >= nr_cpu_ids)
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cpu = cpumask_first(affinity);
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node = cpu_to_node(cpu);
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/*
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* For single allocations we use the caller provided
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* mask otherwise we use the mask of the target cpu
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*/
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mask = cnt == 1 ? affinity : cpumask_of(cpu);
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node = cpu_to_node(cpumask_first(affinity));
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mask = affinity;
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affinity++;
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}
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desc = alloc_desc(start + i, node, flags, mask, owner);
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if (!desc)
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@ -481,9 +480,9 @@ EXPORT_SYMBOL_GPL(irq_free_descs);
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* @cnt: Number of consecutive irqs to allocate.
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* @node: Preferred node on which the irq descriptor should be allocated
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* @owner: Owning module (can be NULL)
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* @affinity: Optional pointer to an affinity mask which hints where the
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* irq descriptors should be allocated and which default
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* affinities to use
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* @affinity: Optional pointer to an affinity mask array of size @cnt which
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* hints where the irq descriptors should be allocated and which
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* default affinities to use
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*
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* Returns the first irq number or error code
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*/
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