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drivers/rtc/rtc-pl031.c: fix the missing operation on enable

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The RTC control register should be enabled in the process of
initializing.

Without this patch, I failed to enable RTC in Hisilicon Hi3620 SoC.  The
register mapping section in RTC is always read as zero.  So I doubt that
ST guys may already enable this register in bootloader.  So they won't
meet this issue.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Haojian Zhuang 2013-02-04 14:28:54 -08:00 committed by Linus Torvalds
parent 72fca4a4b3
commit e7e034e18a
1 changed files with 5 additions and 3 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

8
drivers/rtc/rtc-pl031.c
View file

@ -44,6 +44,7 @@
#define RTC_YMR 0x34 /* Year match register */ #define RTC_YMR 0x34 /* Year match register */
#define RTC_YLR 0x38 /* Year data load register */ #define RTC_YLR 0x38 /* Year data load register */
#define RTC_CR_EN (1 << 0) /* counter enable bit */
#define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */ #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */
#define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */ #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */
@ -320,7 +321,7 @@ static int pl031_probe(struct amba_device *adev, const struct amba_id *id)
struct pl031_local *ldata; struct pl031_local *ldata;
struct pl031_vendor_data *vendor = id->data; struct pl031_vendor_data *vendor = id->data;
struct rtc_class_ops *ops = &vendor->ops; struct rtc_class_ops *ops = &vendor->ops;
unsigned long time; unsigned long time, data;
ret = amba_request_regions(adev, NULL); ret = amba_request_regions(adev, NULL);
if (ret) if (ret)
@ -345,10 +346,11 @@ static int pl031_probe(struct amba_device *adev, const struct amba_id *id)
dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev)); dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev));
dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev)); dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev));
data = readl(ldata->base + RTC_CR);
/* Enable the clockwatch on ST Variants */ /* Enable the clockwatch on ST Variants */
if (vendor->clockwatch) if (vendor->clockwatch)
writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN, data |= RTC_CR_CWEN;
ldata->base + RTC_CR); writel(data | RTC_CR_EN, ldata->base + RTC_CR);
/* /*
* On ST PL031 variants, the RTC reset value does not provide correct * On ST PL031 variants, the RTC reset value does not provide correct