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clk: aspeed: revise ast2600 i3c clock and reset
revise the i3c clock and reset control. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Change-Id: I81d00ce3c5c6c22d208ad34855def9df9c0b407d
This commit is contained in:
Dylan Hung
Ryan Chen
parent
a79a8efe70
commit
ed44b8cdfd
4 changed files with 71 additions and 17 deletions
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@ -177,6 +177,32 @@ config ASPEED_BT_IPMI_BMC
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found on Aspeed SOCs (AST2400 and AST2500). The driver
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implements the BMC side of the BT interface.
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config SSIF_IPMI_BMC
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tristate "SSIF IPMI BMC driver"
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select I2C
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select I2C_SLAVE
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help
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This enables the IPMI SMBus system interface (SSIF) at the
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management (BMC) side.
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The driver implements the BMC side of the SMBus system
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interface (SSIF).
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config ASPEED_SSIF_IPMI_BMC
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depends on ARCH_ASPEED || COMPILE_TEST
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select SSIF_IPMI_BMC
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tristate "Aspeed SSIF IPMI BMC driver"
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help
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Provides a driver for the SSIF IPMI interface found on
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Aspeed AST2500 SoC.
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The driver implements the BMC side of the SMBus system
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interface (SSIF), specific for Aspeed AST2500 SoC.
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The driver implements the BMC side of
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the IPMI over SSIF interface.
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config IPMB_DEVICE_INTERFACE
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tristate 'IPMB Interface handler'
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depends on I2C
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@ -30,3 +30,5 @@ obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o
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obj-$(CONFIG_ASPEED_KCS_IPMI_BMC) += kcs_bmc_aspeed.o
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obj-$(CONFIG_NPCM7XX_KCS_IPMI_BMC) += kcs_bmc_npcm7xx.o
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obj-$(CONFIG_IPMB_DEVICE_INTERFACE) += ipmb_dev_int.o
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obj-$(CONFIG_SSIF_IPMI_BMC) += ssif_bmc.o
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obj-$(CONFIG_ASPEED_SSIF_IPMI_BMC) += ssif_bmc_aspeed.o
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@ -4,6 +4,7 @@
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#define pr_fmt(fmt) "clk-ast2600: " fmt
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#include <linux/bitfield.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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@ -33,6 +34,17 @@
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#define ASPEED_G6_CLK_SELECTION2 0x304
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#define ASPEED_G6_CLK_SELECTION4 0x310
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#define ASPEED_G6_CLK_SELECTION5 0x314
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#define I3C_CLK_SELECTION BIT(31)
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#define I3C_CLK_SELECT_HCLK 0
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#define I3C_CLK_SELECT_APLL_DIV 1
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#define APLL_DIV_SELECTION GENMASK(30, 28)
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#define APLL_DIV_2 0b001
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#define APLL_DIV_3 0b010
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#define APLL_DIV_4 0b011
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#define APLL_DIV_5 0b100
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#define APLL_DIV_6 0b101
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#define APLL_DIV_7 0b110
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#define APLL_DIV_8 0b111
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#define ASPEED_HPLL_PARAM 0x200
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#define ASPEED_APLL_PARAM 0x210
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@ -151,14 +163,14 @@ static struct aspeed_gate_data aspeed_g6_gates[] = {
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[ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
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/* Reserved 38 RSA: no longer used */
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/* Reserved 39 */
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[ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
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[ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
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[ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
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[ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
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[ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
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[ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
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[ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
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[ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
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[ASPEED_CLK_GATE_I3CDMACLK] = { 39, ASPEED_RESET_I3C, "i3cclk-gate", NULL, 0 }, /* I3C_DMA */
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[ASPEED_CLK_GATE_I3C0CLK] = { 40, ASPEED_RESET_I3C0, "i3c0clk-gate", "i3cclk", 0 },
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[ASPEED_CLK_GATE_I3C1CLK] = { 41, ASPEED_RESET_I3C1, "i3c1clk-gate", "i3cclk", 0 },
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[ASPEED_CLK_GATE_I3C2CLK] = { 42, ASPEED_RESET_I3C2, "i3c2clk-gate", "i3cclk", 0 },
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[ASPEED_CLK_GATE_I3C3CLK] = { 43, ASPEED_RESET_I3C3, "i3c3clk-gate", "i3cclk", 0 },
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[ASPEED_CLK_GATE_I3C4CLK] = { 44, ASPEED_RESET_I3C4, "i3c4clk-gate", "i3cclk", 0 },
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[ASPEED_CLK_GATE_I3C5CLK] = { 45, ASPEED_RESET_I3C5, "i3c5clk-gate", "i3cclk", 0 },
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[ASPEED_CLK_GATE_RESERVED44] = { 46, ASPEED_RESET_RESERVED46, "reserved-46", NULL, 0 },
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[ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uxclk", CLK_IS_CRITICAL }, /* UART1 */
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[ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uxclk", CLK_IS_CRITICAL }, /* UART2 */
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[ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uxclk", 0 }, /* UART3 */
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@ -964,6 +976,21 @@ static void __init aspeed_g6_cc(struct regmap *map)
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hw = clk_hw_register_fixed_factor(NULL, "huxclk", "uartx", 0, mult, div);
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aspeed_g6_clk_data->hws[ASPEED_CLK_HUXCLK] = hw;
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/* i3c clock */
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regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val);
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if (FIELD_GET(I3C_CLK_SELECTION, val) == I3C_CLK_SELECT_APLL_DIV) {
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val = FIELD_GET(APLL_DIV_SELECTION, val);
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if (val)
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div = val + 1;
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else
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div = val + 2;
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hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1,
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div);
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} else {
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hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "ahb", 0, 1,
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1);
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}
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aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw;
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};
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static void __init aspeed_g6_cc_init(struct device_node *np)
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@ -51,15 +51,14 @@
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#define ASPEED_CLK_GATE_SDCLK 35
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#define ASPEED_CLK_GATE_EMMCCLK 36
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#define ASPEED_CLK_GATE_I3C0CLK 37
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#define ASPEED_CLK_GATE_I3C1CLK 38
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#define ASPEED_CLK_GATE_I3C2CLK 39
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#define ASPEED_CLK_GATE_I3C3CLK 40
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#define ASPEED_CLK_GATE_I3C4CLK 41
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#define ASPEED_CLK_GATE_I3C5CLK 42
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#define ASPEED_CLK_GATE_I3C6CLK 43
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#define ASPEED_CLK_GATE_I3C7CLK 44
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#define ASPEED_CLK_GATE_I3CDMACLK 37
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#define ASPEED_CLK_GATE_I3C0CLK 38
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#define ASPEED_CLK_GATE_I3C1CLK 39
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#define ASPEED_CLK_GATE_I3C2CLK 40
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#define ASPEED_CLK_GATE_I3C3CLK 41
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#define ASPEED_CLK_GATE_I3C4CLK 42
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#define ASPEED_CLK_GATE_I3C5CLK 43
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#define ASPEED_CLK_GATE_RESERVED44 44
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#define ASPEED_CLK_GATE_FSICLK 45
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#define ASPEED_CLK_HPLL 46
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