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MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes

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The mips_cps_boot_vpes function previously included code to retrieve
pointers to the core & VPE boot configuration structs. These structures
were used both by mips_cps_boot_vpes and by its mips_cps_core_entry
callsite. In preparation for skipping the call to mips_cps_boot_vpes on
some invocations of mips_cps_core_entry, pull the calculation of those
pointers out into a separate function such that it can continue to be
shared.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12337/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2016-02-03 03:15:31 +00:00 committed by Ralf Baechle
parent 3dbc997161
commit f12401d721
3 changed files with 52 additions and 31 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

2
arch/mips/include/asm/smp-cps.h
View file

@ -29,7 +29,7 @@ extern struct core_boot_config *mips_cps_core_bootcfg;
extern void mips_cps_core_entry(void);
extern void mips_cps_core_init(void);
extern struct vpe_boot_config *mips_cps_boot_vpes(void);
extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
extern void mips_cps_pm_save(void);
extern void mips_cps_pm_restore(void);

74
arch/mips/kernel/cps-vec.S
View file

@ -60,6 +60,17 @@
nop
.endm
/* Calculate an uncached address for the CM GCRs */
.macro cmgcrb dest
.set push
.set noat
MFC0 $1, CP0_CMGCRBASE
PTR_SLL $1, $1, 4
PTR_LI \dest, UNCAC_BASE
PTR_ADDU \dest, \dest, $1
.set pop
.endm
.section .text.cps-vec
.balign 0x1000
@ -102,13 +113,8 @@ not_nmi:
mtc0 t0, CP0_CONFIG
ehb
/* Calculate an uncached address for the CM GCRs */
MFC0 v1, CP0_CMGCRBASE
PTR_SLL v1, v1, 4
PTR_LI t0, UNCAC_BASE
PTR_ADDU v1, v1, t0
/* Enter the coherent domain */
cmgcrb v1
li t0, 0xff
sw t0, GCR_CL_COHERENCE_OFS(v1)
ehb
@ -128,17 +134,22 @@ not_nmi:
/* Do any EVA initialization if necessary */
eva_init
/* Retrieve boot configuration pointers */
jal mips_cps_get_bootcfg
nop
/*
* Boot any other VPEs within this core that should be online, and
* deactivate this VPE if it should be offline.
*/
move a1, t9
jal mips_cps_boot_vpes
nop
move a0, v0
/* Off we go! */
PTR_L t1, VPEBOOTCFG_PC(v0)
PTR_L gp, VPEBOOTCFG_GP(v0)
PTR_L sp, VPEBOOTCFG_SP(v0)
PTR_L t1, VPEBOOTCFG_PC(v1)
PTR_L gp, VPEBOOTCFG_GP(v1)
PTR_L sp, VPEBOOTCFG_SP(v1)
jr t1
nop
END(mips_cps_core_entry)
@ -258,18 +269,21 @@ LEAF(mips_cps_core_init)
nop
END(mips_cps_core_init)
LEAF(mips_cps_boot_vpes)
/* Retrieve CM base address */
PTR_LA t0, mips_cm_base
PTR_L t0, 0(t0)
/**
* mips_cps_get_bootcfg() - retrieve boot configuration pointers
*
* Returns: pointer to struct core_boot_config in v0, pointer to
* struct vpe_boot_config in v1, VPE ID in t9
*/
LEAF(mips_cps_get_bootcfg)
/* Calculate a pointer to this cores struct core_boot_config */
cmgcrb t0
lw t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
PTR_L t1, 0(t1)
PTR_ADDU t0, t0, t1
PTR_ADDU v0, t0, t1
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
li t9, 0
@ -297,22 +311,27 @@ LEAF(mips_cps_boot_vpes)
1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
li t1, VPEBOOTCFG_SIZE
mul v0, t9, t1
PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
PTR_ADDU v0, v0, ta3
mul v1, t9, t1
PTR_L ta3, COREBOOTCFG_VPECONFIG(v0)
PTR_ADDU v1, v1, ta3
#ifdef CONFIG_MIPS_MT_SMP
/* If the core doesn't support MT then return */
bnez ta2, 1f
nop
jr ra
nop
END(mips_cps_get_bootcfg)
LEAF(mips_cps_boot_vpes)
PTR_L ta2, COREBOOTCFG_VPEMASK(a0)
PTR_L ta3, COREBOOTCFG_VPECONFIG(a0)
#ifdef CONFIG_MIPS_MT
.set push
.set mt
1: /* Enter VPE configuration state */
/* If the core doesn't support MT then return */
has_mt t0, 5f
/* Enter VPE configuration state */
dvpe
PTR_LA t1, 1f
jr.hb t1
@ -323,7 +342,6 @@ LEAF(mips_cps_boot_vpes)
ehb
/* Loop through each VPE */
PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
move t8, ta2
li ta1, 0
@ -400,7 +418,7 @@ LEAF(mips_cps_boot_vpes)
/* Check whether this VPE is meant to be running */
li t0, 1
sll t0, t0, t9
sll t0, t0, a1
and t0, t0, t8
bnez t0, 2f
nop
@ -417,7 +435,7 @@ LEAF(mips_cps_boot_vpes)
#endif /* CONFIG_MIPS_MT_SMP */
/* Return */
jr ra
5: jr ra
nop
END(mips_cps_boot_vpes)

7
arch/mips/kernel/smp-cps.c
View file

@ -250,7 +250,10 @@ static void boot_core(unsigned core)
static void remote_vpe_boot(void *dummy)
{
mips_cps_boot_vpes();
unsigned core = current_cpu_data.core;
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
}
static void cps_boot_secondary(int cpu, struct task_struct *idle)
@ -296,7 +299,7 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
BUG_ON(!cpu_has_mipsmt);
/* Boot a VPE on this core */
mips_cps_boot_vpes();
mips_cps_boot_vpes(core_cfg, vpe_id);
out:
preempt_enable();
}