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gpio: zynq: fix zynqmp_gpio not an immutable chip warning

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Make the struct irq_chip const and flag it as IRQCHIP_IMMUTABLE,
call gpiochip_disable_irq() in the .irq_mask() callback and
gpiochip_enable_irq() in the .irq_unmask() callback to fix
"gpio gpiochip1: (zynqmp_gpio): not an immutable chip" warning.

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Manikanta Guntupalli 2023-06-09 00:12:52 +05:30 committed by Bartosz Golaszewski
parent 8507f35447
commit f569143935
1 changed files with 15 additions and 7 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

22
drivers/gpio/gpio-zynq.c
View file

@ -151,8 +151,8 @@ struct zynq_platform_data {
int bank_max[ZYNQMP_GPIO_MAX_BANK]; int bank_max[ZYNQMP_GPIO_MAX_BANK];
}; };
static struct irq_chip zynq_gpio_level_irqchip; static const struct irq_chip zynq_gpio_level_irqchip;
static struct irq_chip zynq_gpio_edge_irqchip; static const struct irq_chip zynq_gpio_edge_irqchip;
/** /**
* zynq_gpio_is_zynq - test if HW is zynq or zynqmp * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
@ -404,9 +404,12 @@ static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
static void zynq_gpio_irq_mask(struct irq_data *irq_data) static void zynq_gpio_irq_mask(struct irq_data *irq_data)
{ {
unsigned int device_pin_num, bank_num, bank_pin_num; unsigned int device_pin_num, bank_num, bank_pin_num;
const unsigned long offset = irqd_to_hwirq(irq_data);
struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);
struct zynq_gpio *gpio = struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
gpiochip_disable_irq(chip, offset);
device_pin_num = irq_data->hwirq; device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
writel_relaxed(BIT(bank_pin_num), writel_relaxed(BIT(bank_pin_num),
@ -425,9 +428,12 @@ static void zynq_gpio_irq_mask(struct irq_data *irq_data)
static void zynq_gpio_irq_unmask(struct irq_data *irq_data) static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
{ {
unsigned int device_pin_num, bank_num, bank_pin_num; unsigned int device_pin_num, bank_num, bank_pin_num;
const unsigned long offset = irqd_to_hwirq(irq_data);
struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);
struct zynq_gpio *gpio = struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
gpiochip_enable_irq(chip, offset);
device_pin_num = irq_data->hwirq; device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
writel_relaxed(BIT(bank_pin_num), writel_relaxed(BIT(bank_pin_num),
@ -590,7 +596,7 @@ static void zynq_gpio_irq_relres(struct irq_data *d)
} }
/* irq chip descriptor */ /* irq chip descriptor */
static struct irq_chip zynq_gpio_level_irqchip = { static const struct irq_chip zynq_gpio_level_irqchip = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.irq_enable = zynq_gpio_irq_enable, .irq_enable = zynq_gpio_irq_enable,
.irq_eoi = zynq_gpio_irq_ack, .irq_eoi = zynq_gpio_irq_ack,
@ -601,10 +607,11 @@ static struct irq_chip zynq_gpio_level_irqchip = {
.irq_request_resources = zynq_gpio_irq_reqres, .irq_request_resources = zynq_gpio_irq_reqres,
.irq_release_resources = zynq_gpio_irq_relres, .irq_release_resources = zynq_gpio_irq_relres,
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
IRQCHIP_MASK_ON_SUSPEND, IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
}; };
static struct irq_chip zynq_gpio_edge_irqchip = { static const struct irq_chip zynq_gpio_edge_irqchip = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.irq_enable = zynq_gpio_irq_enable, .irq_enable = zynq_gpio_irq_enable,
.irq_ack = zynq_gpio_irq_ack, .irq_ack = zynq_gpio_irq_ack,
@ -614,7 +621,8 @@ static struct irq_chip zynq_gpio_edge_irqchip = {
.irq_set_wake = zynq_gpio_set_wake, .irq_set_wake = zynq_gpio_set_wake,
.irq_request_resources = zynq_gpio_irq_reqres, .irq_request_resources = zynq_gpio_irq_reqres,
.irq_release_resources = zynq_gpio_irq_relres, .irq_release_resources = zynq_gpio_irq_relres,
.flags = IRQCHIP_MASK_ON_SUSPEND, .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
}; };
static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
@ -962,7 +970,7 @@ static int zynq_gpio_probe(struct platform_device *pdev)
/* Set up the GPIO irqchip */ /* Set up the GPIO irqchip */
girq = &chip->irq; girq = &chip->irq;
girq->chip = &zynq_gpio_edge_irqchip; gpio_irq_chip_set_chip(girq, &zynq_gpio_edge_irqchip);
girq->parent_handler = zynq_gpio_irqhandler; girq->parent_handler = zynq_gpio_irqhandler;
girq->num_parents = 1; girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1, girq->parents = devm_kcalloc(&pdev->dev, 1,