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gpio: add a driver for GPIO pins found on AMD-8111 south bridge chips
Add a driver to use GPIO pins available on several AMD south bridges (currently only AMD 8111 is supported). Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Dmitry Eremin-Solenikov
Linus Walleij
parent
5e67cc4041
commit
f942a7de04
3 changed files with 259 additions and 0 deletions
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@ -466,6 +466,18 @@ config GPIO_BT8XX
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If unsure, say N.
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config GPIO_AMD8111
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tristate "AMD 8111 GPIO driver"
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depends on PCI
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help
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The AMD 8111 south bridge contains 32 GPIO pins which can be used.
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Note, that usually system firmware/ACPI handles GPIO pins on their
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own and users might easily break their systems with uncarefull usage
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of this driver!
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If unsure, say N
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config GPIO_LANGWELL
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bool "Intel Langwell/Penwell GPIO support"
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depends on PCI && X86
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@ -12,6 +12,7 @@ obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
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obj-$(CONFIG_GPIO_AB8500) += gpio-ab8500.o
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obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
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obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
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obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
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obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
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obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
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obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
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246
drivers/gpio/gpio-amd8111.c
Normal file
246
drivers/gpio/gpio-amd8111.c
Normal file
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@ -0,0 +1,246 @@
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/*
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* GPIO driver for AMD 8111 south bridges
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*
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* Copyright (c) 2012 Dmitry Eremin-Solenikov
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*
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* Based on the AMD RNG driver:
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* Copyright 2005 (c) MontaVista Software, Inc.
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* with the majority of the code coming from:
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*
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* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
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* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
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*
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* derived from
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*
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* Hardware driver for the AMD 768 Random Number Generator (RNG)
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* (c) Copyright 2001 Red Hat Inc
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*
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* derived from
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*
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* Hardware driver for Intel i810 Random Number Generator (RNG)
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* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#define PMBASE_OFFSET 0xb0
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#define PMBASE_SIZE 0x30
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#define AMD_REG_GPIO(i) (0x10 + (i))
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#define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
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#define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */
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#define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */
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#define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */
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#define AMD_GPIO_MODE_IN 0x00
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#define AMD_GPIO_MODE_OUT 0x04
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/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
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#define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */
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#define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */
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#define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */
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#define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */
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#define AMD_GPIO_X_OUT_LOW 0x00
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#define AMD_GPIO_X_OUT_HI 0x01
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#define AMD_GPIO_X_OUT_CLK0 0x02
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#define AMD_GPIO_X_OUT_CLK1 0x03
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because someone else might one day
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* want to register another driver on the same PCI id.
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*/
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static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
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{ 0, }, /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, pci_tbl);
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struct amd_gpio {
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struct gpio_chip chip;
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u32 pmbase;
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void __iomem *pm;
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struct pci_dev *pdev;
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spinlock_t lock; /* guards hw registers and orig table */
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u8 orig[32];
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};
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#define to_agp(chip) container_of(chip, struct amd_gpio, chip)
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static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct amd_gpio *agp = to_agp(chip);
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agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
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(AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);
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dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
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return 0;
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}
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static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct amd_gpio *agp = to_agp(chip);
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dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
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iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
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}
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static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct amd_gpio *agp = to_agp(chip);
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u8 temp;
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unsigned long flags;
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spin_lock_irqsave(&agp->lock, flags);
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temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
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temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
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iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
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spin_unlock_irqrestore(&agp->lock, flags);
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dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
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}
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static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct amd_gpio *agp = to_agp(chip);
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u8 temp;
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temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
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dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
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return (temp & AMD_GPIO_RTIN) ? 1 : 0;
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}
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static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct amd_gpio *agp = to_agp(chip);
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u8 temp;
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unsigned long flags;
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spin_lock_irqsave(&agp->lock, flags);
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temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
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temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
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iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
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spin_unlock_irqrestore(&agp->lock, flags);
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dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
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return 0;
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}
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static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
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{
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struct amd_gpio *agp = to_agp(chip);
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u8 temp;
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unsigned long flags;
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spin_lock_irqsave(&agp->lock, flags);
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temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
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temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
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iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
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spin_unlock_irqrestore(&agp->lock, flags);
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dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
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return 0;
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}
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static struct amd_gpio gp = {
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.chip = {
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.label = "AMD GPIO",
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.owner = THIS_MODULE,
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.base = -1,
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.ngpio = 32,
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.request = amd_gpio_request,
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.free = amd_gpio_free,
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.set = amd_gpio_set,
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.get = amd_gpio_get,
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.direction_output = amd_gpio_dirout,
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.direction_input = amd_gpio_dirin,
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},
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};
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static int __init amd_gpio_init(void)
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{
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int err = -ENODEV;
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struct pci_dev *pdev = NULL;
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const struct pci_device_id *ent;
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/* We look for our device - AMD South Bridge
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* I don't know about a system with two such bridges,
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* so we can assume that there is max. one device.
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*
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* We can't use plain pci_driver mechanism,
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* as the device is really a multiple function device,
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* main driver that binds to the pci_device is an smbus
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* driver and have to find & bind to the device this way.
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*/
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for_each_pci_dev(pdev) {
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ent = pci_match_id(pci_tbl, pdev);
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if (ent)
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goto found;
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}
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/* Device not found. */
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goto out;
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found:
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err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
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if (err)
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goto out;
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err = -EIO;
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gp.pmbase &= 0x0000FF00;
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if (gp.pmbase == 0)
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goto out;
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if (!request_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE, "AMD GPIO")) {
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dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
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gp.pmbase + PMBASE_OFFSET);
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err = -EBUSY;
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goto out;
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}
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gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
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gp.pdev = pdev;
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gp.chip.dev = &pdev->dev;
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spin_lock_init(&gp.lock);
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printk(KERN_INFO "AMD-8111 GPIO detected\n");
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err = gpiochip_add(&gp.chip);
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if (err) {
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printk(KERN_ERR "GPIO registering failed (%d)\n",
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err);
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release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
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goto out;
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}
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out:
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return err;
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}
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static void __exit amd_gpio_exit(void)
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{
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int err = gpiochip_remove(&gp.chip);
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WARN_ON(err);
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ioport_unmap(gp.pm);
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release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
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}
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module_init(amd_gpio_init);
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module_exit(amd_gpio_exit);
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MODULE_AUTHOR("The Linux Kernel team");
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MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
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MODULE_LICENSE("GPL");
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