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drm/amdgpu/userq: rework driver parameter

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Replace disable_kq parameter with user_queue parameter.
The parameter has the following logic:
 -1 = auto (ASIC specific default)
  0 = user queues disabled
  1 = user queues enabled and kernel queues enabled (if supported)
  2 = user queues enabled and kernel queues disabled

The default behavior (-1) is currently the same as 0 for current
ASICs.  To enable user queues (in addition to kernel queues) set
user_queue=1. To enable user queues and disable kernel queues
(to make all resources available to user queues), set user_queue=2.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2025-04-14 14:18:03 -04:00
parent 172494c4e9
commit fb20954c97
8 changed files with 77 additions and 16 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View file

@ -271,7 +271,7 @@ extern int amdgpu_agp;
extern int amdgpu_rebar; extern int amdgpu_rebar;
extern int amdgpu_wbrf; extern int amdgpu_wbrf;
extern int amdgpu_disable_kq; extern int amdgpu_user_queue;
#define AMDGPU_VM_MAX_NUM_CTX 4096 #define AMDGPU_VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD (256*1024*1024) #define AMDGPU_SG_THRESHOLD (256*1024*1024)

15
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -242,7 +242,7 @@ int amdgpu_wbrf = -1;
int amdgpu_damage_clips = -1; /* auto */ int amdgpu_damage_clips = -1; /* auto */
int amdgpu_umsch_mm_fwlog; int amdgpu_umsch_mm_fwlog;
int amdgpu_rebar = -1; /* auto */ int amdgpu_rebar = -1; /* auto */
int amdgpu_disable_kq = -1; int amdgpu_user_queue = -1;
DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
"DRM_UT_CORE", "DRM_UT_CORE",
@ -1114,12 +1114,15 @@ MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = en
module_param_named(rebar, amdgpu_rebar, int, 0444); module_param_named(rebar, amdgpu_rebar, int, 0444);
/** /**
* DOC: disable_kq (int) * DOC: user_queue (int)
* Disable kernel queues on systems that support user queues. * Enable user queues on systems that support user queues.
* (0 = kernel queues enabled, 1 = kernel queues disabled, -1 = auto (default setting)) * -1 = auto (ASIC specific default)
* 0 = user queues disabled
* 1 = user queues enabled and kernel queues enabled (if supported)
* 2 = user queues enabled and kernel queues disabled
*/ */
MODULE_PARM_DESC(disable_kq, "Disable kernel queues (-1 = auto (default), 0 = enable KQ, 1 = disable KQ)"); MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
module_param_named(disable_kq, amdgpu_disable_kq, int, 0444); module_param_named(user_queue, amdgpu_user_queue, int, 0444);
/* These devices are not supported by amdgpu. /* These devices are not supported by amdgpu.
* They are supported by the mach64, r128, radeon drivers * They are supported by the mach64, r128, radeon drivers

1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
View file

@ -487,6 +487,7 @@ struct amdgpu_gfx {
struct mutex workload_profile_mutex; struct mutex workload_profile_mutex;
bool disable_kq; bool disable_kq;
bool disable_uq;
}; };
struct amdgpu_gfx_ras_reg_entry { struct amdgpu_gfx_ras_reg_entry {

1
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
View file

@ -138,6 +138,7 @@ struct amdgpu_sdma {
uint32_t supported_reset; uint32_t supported_reset;
struct list_head reset_callback_list; struct list_head reset_callback_list;
bool no_user_submission; bool no_user_submission;
bool disable_uq;
}; };
/* /*

20
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View file

@ -1632,7 +1632,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 0, 3): case IP_VERSION(11, 0, 3):
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */ /* add firmware version checks here */
if (0) { if (0 && !adev->gfx.disable_uq) {
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
} }
@ -1646,7 +1646,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 5, 3): case IP_VERSION(11, 5, 3):
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */ /* add firmware version checks here */
if (0) { if (0 && !adev->gfx.disable_uq) {
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
} }
@ -5211,8 +5211,22 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
{ {
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_disable_kq == 1) switch (amdgpu_user_queue) {
case -1:
case 0:
default:
adev->gfx.disable_kq = false;
adev->gfx.disable_uq = true;
break;
case 1:
adev->gfx.disable_kq = false;
adev->gfx.disable_uq = false;
break;
case 2:
adev->gfx.disable_kq = true; adev->gfx.disable_kq = true;
adev->gfx.disable_uq = false;
break;
}
adev->gfx.funcs = &gfx_v11_0_gfx_funcs; adev->gfx.funcs = &gfx_v11_0_gfx_funcs;

18
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
View file

@ -1418,7 +1418,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(12, 0, 1): case IP_VERSION(12, 0, 1):
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */ /* add firmware version checks here */
if (0) { if (0 && !adev->gfx.disable_uq) {
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
} }
@ -3819,8 +3819,22 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
{ {
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_disable_kq == 1) switch (amdgpu_user_queue) {
case -1:
case 0:
default:
adev->gfx.disable_kq = false;
adev->gfx.disable_uq = true;
break;
case 1:
adev->gfx.disable_kq = false;
adev->gfx.disable_uq = false;
break;
case 2:
adev->gfx.disable_kq = true; adev->gfx.disable_kq = true;
adev->gfx.disable_uq = false;
break;
}
adev->gfx.funcs = &gfx_v12_0_gfx_funcs; adev->gfx.funcs = &gfx_v12_0_gfx_funcs;

18
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
View file

@ -1269,8 +1269,22 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
int r; int r;
if (amdgpu_disable_kq == 1) switch (amdgpu_user_queue) {
case -1:
case 0:
default:
adev->sdma.no_user_submission = false;
adev->sdma.disable_uq = true;
break;
case 1:
adev->sdma.no_user_submission = false;
adev->sdma.disable_uq = false;
break;
case 2:
adev->sdma.no_user_submission = true; adev->sdma.no_user_submission = true;
adev->sdma.disable_uq = false;
break;
}
r = amdgpu_sdma_init_microcode(adev, 0, true); r = amdgpu_sdma_init_microcode(adev, 0, true);
if (r) if (r)
@ -1351,7 +1365,7 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */ /* add firmware version checks here */
if (0) if (0 && !adev->sdma.disable_uq)
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
#endif #endif
r = amdgpu_sdma_sysfs_reset_mask_init(adev); r = amdgpu_sdma_sysfs_reset_mask_init(adev);

18
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
View file

@ -1254,8 +1254,22 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
int r; int r;
if (amdgpu_disable_kq == 1) switch (amdgpu_user_queue) {
case -1:
case 0:
default:
adev->sdma.no_user_submission = false;
adev->sdma.disable_uq = true;
break;
case 1:
adev->sdma.no_user_submission = false;
adev->sdma.disable_uq = false;
break;
case 2:
adev->sdma.no_user_submission = true; adev->sdma.no_user_submission = true;
adev->sdma.disable_uq = false;
break;
}
r = amdgpu_sdma_init_microcode(adev, 0, true); r = amdgpu_sdma_init_microcode(adev, 0, true);
if (r) { if (r) {
@ -1326,7 +1340,7 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */ /* add firmware version checks here */
if (0) if (0 && !adev->sdma.disable_uq)
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
#endif #endif