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drm/amdgpu: add reset_ras_error_count function for MMHUB

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MMHUB ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2020-03-02 12:14:20 +08:00 committed by Alex Deucher
parent 86153f1be2
commit fe5211f19a
4 changed files with 28 additions and 0 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
View file

@ -26,6 +26,7 @@ struct amdgpu_mmhub_funcs {
int (*ras_late_init)(struct amdgpu_device *adev); int (*ras_late_init)(struct amdgpu_device *adev);
void (*query_ras_error_count)(struct amdgpu_device *adev, void (*query_ras_error_count)(struct amdgpu_device *adev,
void *ras_error_status); void *ras_error_status);
void (*reset_ras_error_count)(struct amdgpu_device *adev);
}; };
struct amdgpu_mmhub { struct amdgpu_mmhub {

3
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View file

@ -948,6 +948,9 @@ static int gmc_v9_0_late_init(void *handle)
} }
} }
if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
adev->mmhub.funcs->reset_ras_error_count(adev);
r = amdgpu_gmc_ras_late_init(adev); r = amdgpu_gmc_ras_late_init(adev);
if (r) if (r)
return r; return r;

12
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View file

@ -747,7 +747,19 @@ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
err_data->ue_count += ded_count; err_data->ue_count += ded_count;
} }
static void mmhub_v1_0_reset_ras_error_count(struct amdgpu_device *adev)
{
uint32_t i;
/* read back edc counter registers to reset the counters to 0 */
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++)
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
}
}
const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = { const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
.ras_late_init = amdgpu_mmhub_ras_late_init, .ras_late_init = amdgpu_mmhub_ras_late_init,
.query_ras_error_count = mmhub_v1_0_query_ras_error_count, .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
.reset_ras_error_count = mmhub_v1_0_reset_ras_error_count,
}; };

12
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
View file

@ -1596,7 +1596,19 @@ static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
err_data->ue_count += ded_count; err_data->ue_count += ded_count;
} }
static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
{
uint32_t i;
/* read back edc counter registers to reset the counters to 0 */
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
}
}
const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = { const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
.ras_late_init = amdgpu_mmhub_ras_late_init, .ras_late_init = amdgpu_mmhub_ras_late_init,
.query_ras_error_count = mmhub_v9_4_query_ras_error_count, .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
.reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
}; };