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mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation
These new helpers + macro definitions are meant to replace the old ones which are unpractical to use. Note that the macros and function prefixes have been intentionally changed to ATMEL_[H]SMC_XX and atmel_[h]smc_ to reflect the fact that this IP is also embedded in avr32 SoCs (and not only in at91 ones). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Boris Brezillon
Lee Jones
parent
119d53d44c
commit
fe9d7cb22e
4 changed files with 406 additions and 0 deletions
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@ -121,6 +121,10 @@ config MFD_ATMEL_HLCDC
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additional drivers must be enabled in order to use the
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additional drivers must be enabled in order to use the
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functionality of the device.
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functionality of the device.
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config MFD_ATMEL_SMC
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bool
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select MFD_SYSCON
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config MFD_BCM590XX
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config MFD_BCM590XX
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tristate "Broadcom BCM590xx PMUs"
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tristate "Broadcom BCM590xx PMUs"
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select MFD_CORE
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select MFD_CORE
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@ -185,6 +185,7 @@ obj-$(CONFIG_MFD_TPS65090) += tps65090.o
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obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
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obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
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obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o
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obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o
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obj-$(CONFIG_MFD_ATMEL_HLCDC) += atmel-hlcdc.o
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obj-$(CONFIG_MFD_ATMEL_HLCDC) += atmel-hlcdc.o
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obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o
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obj-$(CONFIG_MFD_INTEL_LPSS) += intel-lpss.o
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obj-$(CONFIG_MFD_INTEL_LPSS) += intel-lpss.o
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obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o
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obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o
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obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o
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obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o
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314
drivers/mfd/atmel-smc.c
Normal file
314
drivers/mfd/atmel-smc.c
Normal file
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@ -0,0 +1,314 @@
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/*
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* Atmel SMC (Static Memory Controller) helper functions.
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*
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* Copyright (C) 2017 Atmel
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* Copyright (C) 2017 Free Electrons
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/mfd/syscon/atmel-smc.h>
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/**
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* atmel_smc_cs_conf_init - initialize a SMC CS conf
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* @conf: the SMC CS conf to initialize
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*
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* Set all fields to 0 so that one can start defining a new config.
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*/
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void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
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{
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memset(conf, 0, sizeof(*conf));
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
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/**
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* atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
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* format expected by the SMC engine
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* @ncycles: number of MCK clk cycles
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* @msbpos: position of the MSB part of the timing field
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* @msbwidth: width of the MSB part of the timing field
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* @msbfactor: factor applied to the MSB
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* @encodedval: param used to store the encoding result
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*
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* This function encodes the @ncycles value as described in the datasheet
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* (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
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* helper which called with different parameter depending on the encoding
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* scheme.
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*
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* If the @ncycles value is too big to be encoded, -ERANGE is returned and
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* the encodedval is contains the maximum val. Otherwise, 0 is returned.
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*/
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static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
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unsigned int msbpos,
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unsigned int msbwidth,
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unsigned int msbfactor,
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unsigned int *encodedval)
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{
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unsigned int lsbmask = GENMASK(msbpos - 1, 0);
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unsigned int msbmask = GENMASK(msbwidth - 1, 0);
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unsigned int msb, lsb;
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int ret = 0;
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msb = ncycles / msbfactor;
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lsb = ncycles % msbfactor;
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if (lsb > lsbmask) {
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lsb = 0;
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msb++;
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}
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/*
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* Let's just put the maximum we can if the requested setting does
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* not fit in the register field.
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* We still return -ERANGE in case the caller cares.
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*/
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if (msb > msbmask) {
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msb = msbmask;
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lsb = lsbmask;
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ret = -ERANGE;
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}
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*encodedval = (msb << msbpos) | lsb;
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return ret;
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}
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/**
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* atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
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* specific value
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* @conf: SMC CS conf descriptor
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* @shift: the position of the Txx field in the TIMINGS register
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* @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
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* parameter
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*
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* This function encodes the @ncycles value as described in the datasheet
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* (section "SMC Timings Register"), and then stores the result in the
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* @conf->timings field at @shift position.
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*
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* Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
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* the field, and 0 otherwise.
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*/
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int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
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unsigned int shift, unsigned int ncycles)
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{
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unsigned int val;
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int ret;
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if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
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shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
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shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
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shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
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shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
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return -EINVAL;
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/*
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* The formula described in atmel datasheets (section "HSMC Timings
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* Register"):
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*
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* ncycles = (Txx[3] * 64) + Txx[2:0]
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*/
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ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
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conf->timings &= ~GENMASK(shift + 3, shift);
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conf->timings |= val << shift;
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return ret;
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
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/**
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* atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
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* specific value
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* @conf: SMC CS conf descriptor
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* @shift: the position of the xx_SETUP field in the SETUP register
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* @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP
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* parameter
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*
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* This function encodes the @ncycles value as described in the datasheet
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* (section "SMC Setup Register"), and then stores the result in the
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* @conf->setup field at @shift position.
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*
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* Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
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* the field, and 0 otherwise.
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*/
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int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
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unsigned int shift, unsigned int ncycles)
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{
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unsigned int val;
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int ret;
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if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
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shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
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return -EINVAL;
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/*
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* The formula described in atmel datasheets (section "SMC Setup
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* Register"):
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*
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* ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0]
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*/
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ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
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conf->setup &= ~GENMASK(shift + 7, shift);
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conf->setup |= val << shift;
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return ret;
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
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/**
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* atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
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* specific value
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* @conf: SMC CS conf descriptor
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* @shift: the position of the xx_PULSE field in the PULSE register
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* @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE
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* parameter
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*
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* This function encodes the @ncycles value as described in the datasheet
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* (section "SMC Pulse Register"), and then stores the result in the
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* @conf->setup field at @shift position.
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*
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* Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
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* the field, and 0 otherwise.
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*/
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int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
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unsigned int shift, unsigned int ncycles)
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{
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unsigned int val;
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int ret;
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if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
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shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
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return -EINVAL;
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/*
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* The formula described in atmel datasheets (section "SMC Pulse
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* Register"):
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*
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* ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0]
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*/
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ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
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conf->pulse &= ~GENMASK(shift + 7, shift);
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conf->pulse |= val << shift;
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return ret;
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
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/**
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* atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
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* specific value
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* @conf: SMC CS conf descriptor
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* @shift: the position of the xx_CYCLE field in the CYCLE register
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* @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE
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* parameter
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*
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* This function encodes the @ncycles value as described in the datasheet
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* (section "SMC Pulse Register"), and then stores the result in the
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* @conf->setup field at @shift position.
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*
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* Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
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* the field, and 0 otherwise.
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*/
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int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
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unsigned int shift, unsigned int ncycles)
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{
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unsigned int val;
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int ret;
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if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
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return -EINVAL;
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/*
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* The formula described in atmel datasheets (section "SMC Cycle
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* Register"):
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*
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* ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0]
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*/
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ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
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conf->cycle &= ~GENMASK(shift + 15, shift);
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conf->cycle |= val << shift;
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return ret;
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
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/**
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* atmel_smc_cs_conf_apply - apply an SMC CS conf
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* @regmap: the SMC regmap
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* @cs: the CS id
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* @conf the SMC CS conf to apply
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*
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* Applies an SMC CS configuration.
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* Only valid on at91sam9/avr32 SoCs.
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*/
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void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
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const struct atmel_smc_cs_conf *conf)
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{
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regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
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regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
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regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
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regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
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/**
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* atmel_hsmc_cs_conf_apply - apply an SMC CS conf
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* @regmap: the HSMC regmap
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* @cs: the CS id
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* @conf the SMC CS conf to apply
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*
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* Applies an SMC CS configuration.
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* Only valid on post-sama5 SoCs.
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*/
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void atmel_hsmc_cs_conf_apply(struct regmap *regmap, int cs,
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const struct atmel_smc_cs_conf *conf)
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{
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regmap_write(regmap, ATMEL_HSMC_SETUP(cs), conf->setup);
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regmap_write(regmap, ATMEL_HSMC_PULSE(cs), conf->pulse);
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regmap_write(regmap, ATMEL_HSMC_CYCLE(cs), conf->cycle);
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regmap_write(regmap, ATMEL_HSMC_TIMINGS(cs), conf->timings);
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regmap_write(regmap, ATMEL_HSMC_MODE(cs), conf->mode);
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}
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EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
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/**
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* atmel_smc_cs_conf_get - retrieve the current SMC CS conf
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* @regmap: the SMC regmap
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* @cs: the CS id
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* @conf: the SMC CS conf object to store the current conf
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*
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* Retrieve the SMC CS configuration.
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* Only valid on at91sam9/avr32 SoCs.
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*/
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void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
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struct atmel_smc_cs_conf *conf)
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{
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regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
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regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
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regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
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regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
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}
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EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
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/**
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* atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
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* @regmap: the HSMC regmap
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* @cs: the CS id
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* @conf: the SMC CS conf object to store the current conf
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*
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* Retrieve the SMC CS configuration.
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* Only valid on post-sama5 SoCs.
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*/
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void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs,
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struct atmel_smc_cs_conf *conf)
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{
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regmap_read(regmap, ATMEL_HSMC_SETUP(cs), &conf->setup);
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regmap_read(regmap, ATMEL_HSMC_PULSE(cs), &conf->pulse);
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regmap_read(regmap, ATMEL_HSMC_CYCLE(cs), &conf->cycle);
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regmap_read(regmap, ATMEL_HSMC_TIMINGS(cs), &conf->timings);
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regmap_read(regmap, ATMEL_HSMC_MODE(cs), &conf->mode);
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||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
|
||||||
|
|
@ -69,6 +69,93 @@
|
||||||
#define AT91_SMC_PS_16 (2 << 28)
|
#define AT91_SMC_PS_16 (2 << 28)
|
||||||
#define AT91_SMC_PS_32 (3 << 28)
|
#define AT91_SMC_PS_32 (3 << 28)
|
||||||
|
|
||||||
|
#define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
|
||||||
|
#define ATMEL_HSMC_SETUP(cs) (0x600 + ((cs) * 0x14))
|
||||||
|
#define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
|
||||||
|
#define ATMEL_HSMC_PULSE(cs) (0x600 + ((cs) * 0x14) + 0x4)
|
||||||
|
#define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
|
||||||
|
#define ATMEL_HSMC_CYCLE(cs) (0x600 + ((cs) * 0x14) + 0x8)
|
||||||
|
#define ATMEL_SMC_NWE_SHIFT 0
|
||||||
|
#define ATMEL_SMC_NCS_WR_SHIFT 8
|
||||||
|
#define ATMEL_SMC_NRD_SHIFT 16
|
||||||
|
#define ATMEL_SMC_NCS_RD_SHIFT 24
|
||||||
|
|
||||||
|
#define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
|
||||||
|
#define ATMEL_HSMC_MODE(cs) (0x600 + ((cs) * 0x14) + 0x10)
|
||||||
|
#define ATMEL_SMC_MODE_READMODE_MASK BIT(0)
|
||||||
|
#define ATMEL_SMC_MODE_READMODE_NCS (0 << 0)
|
||||||
|
#define ATMEL_SMC_MODE_READMODE_NRD (1 << 0)
|
||||||
|
#define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1)
|
||||||
|
#define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1)
|
||||||
|
#define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1)
|
||||||
|
#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)
|
||||||
|
#define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4)
|
||||||
|
#define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4)
|
||||||
|
#define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4)
|
||||||
|
#define ATMEL_SMC_MODE_BAT_MASK BIT(8)
|
||||||
|
#define ATMEL_SMC_MODE_BAT_SELECT (0 << 8)
|
||||||
|
#define ATMEL_SMC_MODE_BAT_WRITE (1 << 8)
|
||||||
|
#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)
|
||||||
|
#define ATMEL_SMC_MODE_DBW_8 (0 << 12)
|
||||||
|
#define ATMEL_SMC_MODE_DBW_16 (1 << 12)
|
||||||
|
#define ATMEL_SMC_MODE_DBW_32 (2 << 12)
|
||||||
|
#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)
|
||||||
|
#define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
|
||||||
|
#define ATMEL_SMC_MODE_TDF_MAX 16
|
||||||
|
#define ATMEL_SMC_MODE_TDF_MIN 1
|
||||||
|
#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20)
|
||||||
|
#define ATMEL_SMC_MODE_PMEN BIT(24)
|
||||||
|
#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
|
||||||
|
#define ATMEL_SMC_MODE_PS_4 (0 << 28)
|
||||||
|
#define ATMEL_SMC_MODE_PS_8 (1 << 28)
|
||||||
|
#define ATMEL_SMC_MODE_PS_16 (2 << 28)
|
||||||
|
#define ATMEL_SMC_MODE_PS_32 (3 << 28)
|
||||||
|
|
||||||
|
#define ATMEL_HSMC_TIMINGS(cs) (0x600 + ((cs) * 0x14) + 0xc)
|
||||||
|
#define ATMEL_HSMC_TIMINGS_OCMS BIT(12)
|
||||||
|
#define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28)
|
||||||
|
#define ATMEL_HSMC_TIMINGS_NFSEL BIT(31)
|
||||||
|
#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0
|
||||||
|
#define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4
|
||||||
|
#define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8
|
||||||
|
#define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16
|
||||||
|
#define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
|
||||||
|
* @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200)
|
||||||
|
* @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200)
|
||||||
|
* @cycle: NWE/NRD cycle timings (not applicable to at91rm9200)
|
||||||
|
* @timings: advanced NAND related timings (only applicable to HSMC)
|
||||||
|
* @mode: all kind of config parameters (see the fields definition above).
|
||||||
|
* The mode fields are different on at91rm9200
|
||||||
|
*/
|
||||||
|
struct atmel_smc_cs_conf {
|
||||||
|
u32 setup;
|
||||||
|
u32 pulse;
|
||||||
|
u32 cycle;
|
||||||
|
u32 timings;
|
||||||
|
u32 mode;
|
||||||
|
};
|
||||||
|
|
||||||
|
void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
|
||||||
|
int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
|
||||||
|
unsigned int shift,
|
||||||
|
unsigned int ncycles);
|
||||||
|
int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
|
||||||
|
unsigned int shift, unsigned int ncycles);
|
||||||
|
int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
|
||||||
|
unsigned int shift, unsigned int ncycles);
|
||||||
|
int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
|
||||||
|
unsigned int shift, unsigned int ncycles);
|
||||||
|
void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
|
||||||
|
const struct atmel_smc_cs_conf *conf);
|
||||||
|
void atmel_hsmc_cs_conf_apply(struct regmap *regmap, int cs,
|
||||||
|
const struct atmel_smc_cs_conf *conf);
|
||||||
|
void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
|
||||||
|
struct atmel_smc_cs_conf *conf);
|
||||||
|
void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs,
|
||||||
|
struct atmel_smc_cs_conf *conf);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This function converts a setup timing expressed in nanoseconds into an
|
* This function converts a setup timing expressed in nanoseconds into an
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue