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clk: vt8500: convert from round_rate() to determine_rate()

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The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Brian Masney 2025-08-11 11:18:54 -04:00
parent 9e3372b2eb
commit ff03cca71e
1 changed files with 35 additions and 24 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

59
drivers/clk/clk-vt8500.c
View file

@ -128,30 +128,31 @@ static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
return parent_rate / div; return parent_rate / div;
} }
static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, static int vt8500_dclk_determine_rate(struct clk_hw *hw,
unsigned long *prate) struct clk_rate_request *req)
{ {
struct clk_device *cdev = to_clk_device(hw); struct clk_device *cdev = to_clk_device(hw);
u32 divisor; u32 divisor;
if (rate == 0) if (req->rate == 0)
return 0; return 0;
divisor = *prate / rate; divisor = req->best_parent_rate / req->rate;
/* If prate / rate would be decimal, incr the divisor */ /* If prate / rate would be decimal, incr the divisor */
if (rate * divisor < *prate) if (req->rate * divisor < req->best_parent_rate)
divisor++; divisor++;
/* /*
* If this is a request for SDMMC we have to adjust the divisor * If this is a request for SDMMC we have to adjust the divisor
* when >31 to use the fixed predivisor * when >31 to use the fixed predivisor
*/ */
if ((cdev->div_mask == 0x3F) && (divisor > 31)) { if ((cdev->div_mask == 0x3F) && (divisor > 31))
divisor = 64 * ((divisor / 64) + 1); divisor = 64 * ((divisor / 64) + 1);
}
return *prate / divisor; req->rate = req->best_parent_rate / divisor;
return 0;
} }
static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
@ -202,7 +203,7 @@ static const struct clk_ops vt8500_gated_clk_ops = {
}; };
static const struct clk_ops vt8500_divisor_clk_ops = { static const struct clk_ops vt8500_divisor_clk_ops = {
.round_rate = vt8500_dclk_round_rate, .determine_rate = vt8500_dclk_determine_rate,
.set_rate = vt8500_dclk_set_rate, .set_rate = vt8500_dclk_set_rate,
.recalc_rate = vt8500_dclk_recalc_rate, .recalc_rate = vt8500_dclk_recalc_rate,
}; };
@ -211,7 +212,7 @@ static const struct clk_ops vt8500_gated_divisor_clk_ops = {
.enable = vt8500_dclk_enable, .enable = vt8500_dclk_enable,
.disable = vt8500_dclk_disable, .disable = vt8500_dclk_disable,
.is_enabled = vt8500_dclk_is_enabled, .is_enabled = vt8500_dclk_is_enabled,
.round_rate = vt8500_dclk_round_rate, .determine_rate = vt8500_dclk_determine_rate,
.set_rate = vt8500_dclk_set_rate, .set_rate = vt8500_dclk_set_rate,
.recalc_rate = vt8500_dclk_recalc_rate, .recalc_rate = vt8500_dclk_recalc_rate,
}; };
@ -594,8 +595,8 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0; return 0;
} }
static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, static int vtwm_pll_determine_rate(struct clk_hw *hw,
unsigned long *prate) struct clk_rate_request *req)
{ {
struct clk_pll *pll = to_clk_pll(hw); struct clk_pll *pll = to_clk_pll(hw);
u32 filter, mul, div1, div2; u32 filter, mul, div1, div2;
@ -604,33 +605,43 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
switch (pll->type) { switch (pll->type) {
case PLL_TYPE_VT8500: case PLL_TYPE_VT8500:
ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1); ret = vt8500_find_pll_bits(req->rate, req->best_parent_rate,
&mul, &div1);
if (!ret) if (!ret)
round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); round_rate = VT8500_BITS_TO_FREQ(req->best_parent_rate,
mul, div1);
break; break;
case PLL_TYPE_WM8650: case PLL_TYPE_WM8650:
ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); ret = wm8650_find_pll_bits(req->rate, req->best_parent_rate,
&mul, &div1, &div2);
if (!ret) if (!ret)
round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); round_rate = WM8650_BITS_TO_FREQ(req->best_parent_rate,
mul, div1, div2);
break; break;
case PLL_TYPE_WM8750: case PLL_TYPE_WM8750:
ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); ret = wm8750_find_pll_bits(req->rate, req->best_parent_rate,
&filter, &mul, &div1, &div2);
if (!ret) if (!ret)
round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); round_rate = WM8750_BITS_TO_FREQ(req->best_parent_rate,
mul, div1, div2);
break; break;
case PLL_TYPE_WM8850: case PLL_TYPE_WM8850:
ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2); ret = wm8850_find_pll_bits(req->rate, req->best_parent_rate,
&mul, &div1, &div2);
if (!ret) if (!ret)
round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); round_rate = WM8850_BITS_TO_FREQ(req->best_parent_rate,
mul, div1, div2);
break; break;
default: default:
ret = -EINVAL; return -EINVAL;
} }
if (ret) if (ret)
return ret; req->rate = ret;
else
req->rate = round_rate;
return round_rate; return 0;
} }
static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw, static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
@ -665,7 +676,7 @@ static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
} }
static const struct clk_ops vtwm_pll_ops = { static const struct clk_ops vtwm_pll_ops = {
.round_rate = vtwm_pll_round_rate, .determine_rate = vtwm_pll_determine_rate,
.set_rate = vtwm_pll_set_rate, .set_rate = vtwm_pll_set_rate,
.recalc_rate = vtwm_pll_recalc_rate, .recalc_rate = vtwm_pll_recalc_rate,
}; };