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Author SHA1 Message Date
Dinh Nguyen
44a7f3e822 clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk 
Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-06-19 19:27:33 -07:00
Dinh Nguyen
6f3bcf56f8 clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk 
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-06-19 19:27:33 -07:00
Dinh Nguyen
80c6b7a089 clk: socfpga: agilex: add clock driver for the Agilex platform 
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-05-26 19:13:05 -07:00