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Xilinx 7 series FPGA can be programmed using a parallel port named the SelectMAP interface in the datasheet. This interface is compatible with the i.MX6 EIM bus controller but other types of external memory mapped parallel bus might work. xilinx-selectmap currently only supports the x8 mode where data is loaded at one byte per rising edge of the clock, with the MSb of each byte presented to the D0 pin. Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com> [yilun.xu@linux.intel.com: replace data type of i from u32 to size_t] Acked-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
62 lines
2.3 KiB
Makefile
62 lines
2.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the fpga framework and fpga manager drivers.
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#
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# Core FPGA Manager Framework
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obj-$(CONFIG_FPGA) += fpga-mgr.o
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# FPGA Manager Drivers
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obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
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obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
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obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
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obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
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obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
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obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
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obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
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obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o
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obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o
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obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
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obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
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obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
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obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
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obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o
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obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) += lattice-sysconfig.o
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obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) += lattice-sysconfig-spi.o
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obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
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obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
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# FPGA Secure Update Drivers
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obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) += intel-m10-bmc-sec-update.o
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# FPGA Bridge Drivers
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obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
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obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
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obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
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obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
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# High Level Interfaces
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obj-$(CONFIG_FPGA_REGION) += fpga-region.o
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obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
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# FPGA Device Feature List Support
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obj-$(CONFIG_FPGA_DFL) += dfl.o
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obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
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obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
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obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
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obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
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obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
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dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
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dfl-fme-objs += dfl-fme-perf.o
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dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
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dfl-afu-objs += dfl-afu-error.o
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obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
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# Drivers for FPGAs which implement DFL
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obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
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# KUnit tests
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obj-$(CONFIG_FPGA_KUNIT_TESTS) += tests/
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