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276e8beb2a
Add support for forcing completion of userq fences. This is needed for userq resets and asic resets so that we can set the error on the fence and force completion. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_USERQ_FENCE_H__
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#define __AMDGPU_USERQ_FENCE_H__
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#include <linux/types.h>
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#include "amdgpu_userq.h"
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struct amdgpu_userq_fence {
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struct dma_fence base;
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/*
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* This lock is necessary to synchronize the
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* userqueue dma fence operations.
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*/
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spinlock_t lock;
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struct list_head link;
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unsigned long fence_drv_array_count;
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struct amdgpu_userq_fence_driver *fence_drv;
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struct amdgpu_userq_fence_driver **fence_drv_array;
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};
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struct amdgpu_userq_fence_driver {
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struct kref refcount;
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u64 va;
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u64 gpu_addr;
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u64 *cpu_addr;
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u64 context;
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/*
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* This lock is necesaary to synchronize the access
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* to the fences list by the fence driver.
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*/
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spinlock_t fence_list_lock;
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struct list_head fences;
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struct amdgpu_device *adev;
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char timeline_name[TASK_COMM_LEN];
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};
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int amdgpu_userq_fence_slab_init(void);
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void amdgpu_userq_fence_slab_fini(void);
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void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv);
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void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv);
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int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev,
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struct amdgpu_usermode_queue *userq);
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void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq);
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void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv);
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void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq);
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void amdgpu_userq_fence_driver_destroy(struct kref *ref);
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int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp);
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int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp);
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#endif
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