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7f544c5488
To align with other IP blocks Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_ras.h"
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#include "amdgpu.h"
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#include "amdgpu_mca.h"
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#define smnMCMP0_STATUST0 0x03830408
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#define smnMCMP1_STATUST0 0x03b30408
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#define smnMCMPIO_STATUST0 0x0c930408
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static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_mca_query_ras_error_count(adev,
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smnMCMP0_STATUST0,
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ras_error_status);
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}
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static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
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enum amdgpu_ras_block block, uint32_t sub_block_index)
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{
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if (!block_obj)
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return -EINVAL;
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if ((block_obj->ras_comm.block == block) &&
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(block_obj->ras_comm.sub_block_index == sub_block_index)) {
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return 0;
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}
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return -EINVAL;
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}
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static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
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.query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
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.query_ras_error_address = NULL,
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};
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struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
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.ras_block = {
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.hw_ops = &mca_v3_0_mp0_hw_ops,
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.ras_block_match = mca_v3_0_ras_block_match,
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},
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};
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static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_mca_query_ras_error_count(adev,
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smnMCMP1_STATUST0,
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ras_error_status);
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}
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static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
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.query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
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.query_ras_error_address = NULL,
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};
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struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
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.ras_block = {
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.hw_ops = &mca_v3_0_mp1_hw_ops,
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.ras_block_match = mca_v3_0_ras_block_match,
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},
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};
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static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_mca_query_ras_error_count(adev,
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smnMCMPIO_STATUST0,
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ras_error_status);
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}
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static const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
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.query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
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.query_ras_error_address = NULL,
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};
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struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
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.ras_block = {
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.hw_ops = &mca_v3_0_mpio_hw_ops,
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.ras_block_match = mca_v3_0_ras_block_match,
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},
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};
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