Relja Vojvodic edae98a2bd drm/amd/display: Add DSC padding for OVT Support ... [Why] -Certain OVT timings require DSC configurations which divide the horizontal active unevenly across DSC slices -DSC slices must be even, so padding needs to be added to the active to make this possible -The pixel clock of the HW now needs to be increased to accommodate the extra padded pixels -To keep the line time the same, the blank of the HW timing needs to be increased as well [How] -Calculate h_active padding, h_total padding, and pixel clock based off of the original OVT timing and DSC calculations -Store these values in the pipe and program HW with these modifications -Added general support for cases where DSC slice config does not evenly split the horizontal active by fixing some slice width calculations -Updated PPS calculations for these cases Reviewed-by: Chris Park <chris.park@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Relja Vojvodic <rvojvodi@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2025-09-15 17:01:11 -04:00
..
dcn20	drm/amd/display: Add DSC padding for OVT Support	2025-09-15 17:01:11 -04:00
dcn35
dcn401	drm/amd/display: Refactor DSC cap calculations	2025-07-15 14:07:51 -04:00
dc_dsc.c	drm/amd/display: Consider sink max slice width limitation for dsc	2025-08-27 13:57:50 -04:00
dsc.h	drm/amd/display: Make dcn401_initialize_min_clocks() available to other compilation units	2025-07-15 14:07:51 -04:00
dscc_types.h
Makefile
rc_calc.c
rc_calc.h
rc_calc_dpi.c