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f99f5f3ea7
Read the GPU ID register at probe time and select the correct
features/quirks/enhancements. Use the GPU ID to form the firmware
file name and load the firmware.
The features/quirks/enhancements arrays are currently hardcoded in
the driver for the supported GPUs. We are looking at moving this
information to the firmware image.
Changes since v8:
- Corrected license identifiers
Changes since v7:
- Fix kerneldoc for pvr_device_info_set_enhancements()
Changes since v5:
- Add BRN 71242 to device info
Changes since v4:
- Retrieve device information from firmware header
- Pull forward firmware header parsing from FW infrastructure patch
- Use devm_add_action_or_reset to release firmware
Changes since v3:
- Use drm_dev_{enter,exit}
Co-developed-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Co-developed-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Co-developed-by: Donald Robson <donald.robson@imgtec.com>
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Link: https://lore.kernel.org/r/1ff76f7a5b45c742279c78910f8491b8a5e7f6e6.1700668843.git.donald.robson@imgtec.com
Signed-off-by: Maxime Ripard <mripard@kernel.org>
186 lines
4.7 KiB
C
186 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_DEVICE_INFO_H
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#define PVR_DEVICE_INFO_H
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#include <linux/types.h>
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struct pvr_device;
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/*
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* struct pvr_device_features - Hardware feature information
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*/
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struct pvr_device_features {
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bool has_axi_acelite;
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bool has_cdm_control_stream_format;
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bool has_cluster_grouping;
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bool has_common_store_size_in_dwords;
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bool has_compute;
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bool has_compute_morton_capable;
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bool has_compute_overlap;
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bool has_coreid_per_os;
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bool has_dynamic_dust_power;
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bool has_ecc_rams;
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bool has_fb_cdc_v4;
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bool has_fbc_max_default_descriptors;
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bool has_fbc_max_large_descriptors;
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bool has_fbcdc;
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bool has_fbcdc_algorithm;
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bool has_fbcdc_architecture;
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bool has_gpu_multicore_support;
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bool has_gpu_virtualisation;
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bool has_gs_rta_support;
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bool has_irq_per_os;
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bool has_isp_max_tiles_in_flight;
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bool has_isp_samples_per_pixel;
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bool has_isp_zls_d24_s8_packing_ogl_mode;
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bool has_layout_mars;
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bool has_max_partitions;
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bool has_meta;
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bool has_meta_coremem_size;
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bool has_mips;
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bool has_num_clusters;
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bool has_num_isp_ipp_pipes;
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bool has_num_osids;
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bool has_num_raster_pipes;
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bool has_pbe2_in_xe;
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bool has_pbvnc_coreid_reg;
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bool has_perfbus;
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bool has_perf_counter_batch;
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bool has_phys_bus_width;
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bool has_riscv_fw_processor;
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bool has_roguexe;
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bool has_s7_top_infrastructure;
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bool has_simple_internal_parameter_format;
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bool has_simple_internal_parameter_format_v2;
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bool has_simple_parameter_format_version;
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bool has_slc_banks;
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bool has_slc_cache_line_size_bits;
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bool has_slc_size_configurable;
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bool has_slc_size_in_kilobytes;
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bool has_soc_timer;
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bool has_sys_bus_secure_reset;
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bool has_tessellation;
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bool has_tile_region_protection;
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bool has_tile_size_x;
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bool has_tile_size_y;
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bool has_tla;
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bool has_tpu_cem_datamaster_global_registers;
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bool has_tpu_dm_global_registers;
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bool has_tpu_filtering_mode_control;
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bool has_usc_min_output_registers_per_pix;
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bool has_vdm_drawindirect;
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bool has_vdm_object_level_lls;
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bool has_virtual_address_space_bits;
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bool has_watchdog_timer;
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bool has_workgroup_protection;
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bool has_xe_architecture;
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bool has_xe_memory_hierarchy;
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bool has_xe_tpu2;
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bool has_xpu_max_regbanks_addr_width;
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bool has_xpu_max_slaves;
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bool has_xpu_register_broadcast;
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bool has_xt_top_infrastructure;
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bool has_zls_subtile;
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u64 cdm_control_stream_format;
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u64 common_store_size_in_dwords;
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u64 ecc_rams;
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u64 fbc_max_default_descriptors;
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u64 fbc_max_large_descriptors;
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u64 fbcdc;
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u64 fbcdc_algorithm;
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u64 fbcdc_architecture;
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u64 isp_max_tiles_in_flight;
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u64 isp_samples_per_pixel;
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u64 layout_mars;
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u64 max_partitions;
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u64 meta;
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u64 meta_coremem_size;
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u64 num_clusters;
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u64 num_isp_ipp_pipes;
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u64 num_osids;
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u64 num_raster_pipes;
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u64 phys_bus_width;
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u64 simple_parameter_format_version;
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u64 slc_banks;
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u64 slc_cache_line_size_bits;
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u64 slc_size_in_kilobytes;
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u64 tile_size_x;
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u64 tile_size_y;
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u64 usc_min_output_registers_per_pix;
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u64 virtual_address_space_bits;
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u64 xe_architecture;
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u64 xpu_max_regbanks_addr_width;
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u64 xpu_max_slaves;
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u64 xpu_register_broadcast;
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};
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/*
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* struct pvr_device_quirks - Hardware quirk information
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*/
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struct pvr_device_quirks {
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bool has_brn44079;
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bool has_brn47217;
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bool has_brn48492;
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bool has_brn48545;
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bool has_brn49927;
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bool has_brn50767;
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bool has_brn51764;
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bool has_brn62269;
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bool has_brn63142;
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bool has_brn63553;
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bool has_brn66011;
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bool has_brn71242;
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};
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/*
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* struct pvr_device_enhancements - Hardware enhancement information
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*/
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struct pvr_device_enhancements {
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bool has_ern35421;
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bool has_ern38020;
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bool has_ern38748;
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bool has_ern42064;
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bool has_ern42290;
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bool has_ern42606;
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bool has_ern47025;
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bool has_ern57596;
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};
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void pvr_device_info_set_quirks(struct pvr_device *pvr_dev, const u64 *bitmask,
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u32 bitmask_len);
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void pvr_device_info_set_enhancements(struct pvr_device *pvr_dev, const u64 *bitmask,
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u32 bitmask_len);
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int pvr_device_info_set_features(struct pvr_device *pvr_dev, const u64 *features, u32 features_size,
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u32 feature_param_size);
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/*
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* Meta cores
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*
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* These are the values for the 'meta' feature when the feature is present
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* (as per &struct pvr_device_features)/
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*/
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#define PVR_META_MTP218 (1)
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#define PVR_META_MTP219 (2)
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#define PVR_META_LTP218 (3)
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#define PVR_META_LTP217 (4)
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enum {
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PVR_FEATURE_CDM_USER_MODE_QUEUE,
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PVR_FEATURE_CLUSTER_GROUPING,
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PVR_FEATURE_COMPUTE_MORTON_CAPABLE,
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PVR_FEATURE_FB_CDC_V4,
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PVR_FEATURE_GPU_MULTICORE_SUPPORT,
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PVR_FEATURE_ISP_ZLS_D24_S8_PACKING_OGL_MODE,
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PVR_FEATURE_REQUIRES_FB_CDC_ZLS_SETUP,
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PVR_FEATURE_S7_TOP_INFRASTRUCTURE,
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PVR_FEATURE_TESSELLATION,
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PVR_FEATURE_TPU_DM_GLOBAL_REGISTERS,
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PVR_FEATURE_VDM_DRAWINDIRECT,
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PVR_FEATURE_VDM_OBJECT_LEVEL_LLS,
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PVR_FEATURE_ZLS_SUBTILE,
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};
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#endif /* PVR_DEVICE_INFO_H */
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