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7900e00434
Changes since v8: - Corrected license identifiers Changes since v5: - Split up header commit due to size Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Donald Robson <donald.robson@imgtec.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/23ee233dfbe6f2239328f8201fd6d8c1017cea58.1700668843.git.donald.robson@imgtec.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
335 lines
14 KiB
C
335 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_ROGUE_MIPS_H
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#define PVR_ROGUE_MIPS_H
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#include <linux/bits.h>
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#include <linux/types.h>
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/* Utility defines for memory management. */
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#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K (12)
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#define ROGUE_MIPSFW_PAGE_SIZE_4K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
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#define ROGUE_MIPSFW_PAGE_MASK_4K (ROGUE_MIPSFW_PAGE_SIZE_4K - 1)
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#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K (16)
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#define ROGUE_MIPSFW_PAGE_SIZE_64K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K)
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#define ROGUE_MIPSFW_PAGE_MASK_64K (ROGUE_MIPSFW_PAGE_SIZE_64K - 1)
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#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_256K (18)
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#define ROGUE_MIPSFW_PAGE_SIZE_256K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_256K)
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#define ROGUE_MIPSFW_PAGE_MASK_256K (ROGUE_MIPSFW_PAGE_SIZE_256K - 1)
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#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_1MB (20)
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#define ROGUE_MIPSFW_PAGE_SIZE_1MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_1MB)
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#define ROGUE_MIPSFW_PAGE_MASK_1MB (ROGUE_MIPSFW_PAGE_SIZE_1MB - 1)
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#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_4MB (22)
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#define ROGUE_MIPSFW_PAGE_SIZE_4MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4MB)
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#define ROGUE_MIPSFW_PAGE_MASK_4MB (ROGUE_MIPSFW_PAGE_SIZE_4MB - 1)
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#define ROGUE_MIPSFW_LOG2_PTE_ENTRY_SIZE (2)
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/* log2 page table sizes dependent on FW heap size and page size (for each OS). */
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#define ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_4K(pvr_dev) ((pvr_dev)->fw_dev.fw_heap_info.log2_size - \
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ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K + \
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ROGUE_MIPSFW_LOG2_PTE_ENTRY_SIZE)
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#define ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_64K(pvr_dev) ((pvr_dev)->fw_dev.fw_heap_info.log2_size - \
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ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K + \
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ROGUE_MIPSFW_LOG2_PTE_ENTRY_SIZE)
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/* Maximum number of page table pages (both Host and MIPS pages). */
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#define ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES (4)
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/* Total number of TLB entries. */
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#define ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES (16)
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/* "Uncached" caching policy. */
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#define ROGUE_MIPSFW_UNCACHED_CACHE_POLICY (2)
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/* "Write-back write-allocate" caching policy. */
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#define ROGUE_MIPSFW_WRITEBACK_CACHE_POLICY (3)
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/* "Write-through no write-allocate" caching policy. */
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#define ROGUE_MIPSFW_WRITETHROUGH_CACHE_POLICY (1)
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/* Cached policy used by MIPS in case of physical bus on 32 bit. */
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#define ROGUE_MIPSFW_CACHED_POLICY (ROGUE_MIPSFW_WRITEBACK_CACHE_POLICY)
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/* Cached policy used by MIPS in case of physical bus on more than 32 bit. */
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#define ROGUE_MIPSFW_CACHED_POLICY_ABOVE_32BIT (ROGUE_MIPSFW_WRITETHROUGH_CACHE_POLICY)
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/* Total number of Remap entries. */
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#define ROGUE_MIPSFW_NUMBER_OF_REMAP_ENTRIES (2 * ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES)
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/* MIPS EntryLo/PTE format. */
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#define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U)
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#define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF)
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#define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000)
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#define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U)
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#define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF)
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#define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000)
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/* Page Frame Number */
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#define ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT (6)
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#define ROGUE_MIPSFW_ENTRYLO_PFN_ALIGNSHIFT (12)
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/* Mask used for the MIPS Page Table in case of physical bus on 32 bit. */
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#define ROGUE_MIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0)
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#define ROGUE_MIPSFW_ENTRYLO_PFN_SIZE (20)
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/* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit. */
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#define ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0)
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#define ROGUE_MIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24)
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#define ROGUE_MIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (ROGUE_MIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \
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ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT)
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#define ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U)
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#define ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7)
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#define ROGUE_MIPSFW_ENTRYLO_DIRTY_SHIFT (2U)
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#define ROGUE_MIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB)
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#define ROGUE_MIPSFW_ENTRYLO_DIRTY_EN (0X00000004)
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#define ROGUE_MIPSFW_ENTRYLO_VALID_SHIFT (1U)
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#define ROGUE_MIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD)
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#define ROGUE_MIPSFW_ENTRYLO_VALID_EN (0X00000002)
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#define ROGUE_MIPSFW_ENTRYLO_GLOBAL_SHIFT (0U)
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#define ROGUE_MIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE)
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#define ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN (0X00000001)
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#define ROGUE_MIPSFW_ENTRYLO_DVG (ROGUE_MIPSFW_ENTRYLO_DIRTY_EN | \
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ROGUE_MIPSFW_ENTRYLO_VALID_EN | \
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ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN)
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#define ROGUE_MIPSFW_ENTRYLO_UNCACHED (ROGUE_MIPSFW_UNCACHED_CACHE_POLICY << \
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ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT)
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#define ROGUE_MIPSFW_ENTRYLO_DVG_UNCACHED (ROGUE_MIPSFW_ENTRYLO_DVG | \
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ROGUE_MIPSFW_ENTRYLO_UNCACHED)
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/* Remap Range Config Addr Out. */
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/* These defines refer to the upper half of the Remap Range Config register. */
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#define ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_MASK (0x0FFFFFF0)
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#define ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_SHIFT (4) /* wrt upper half of the register. */
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#define ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_ALIGNSHIFT (12)
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#define ROGUE_MIPSFW_ADDR_TO_RR_ADDR_OUT_RSHIFT (ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_ALIGNSHIFT - \
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ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_SHIFT)
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/*
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* Pages to trampoline problematic physical addresses:
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* - ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN : 0x1FC0_0000
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* - ROGUE_MIPSFW_DATA_REMAP_PHYS_ADDR_IN : 0x1FC0_1000
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* - ROGUE_MIPSFW_CODE_REMAP_PHYS_ADDR_IN : 0x1FC0_2000
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* - (benign trampoline) : 0x1FC0_3000
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* that would otherwise be erroneously remapped by the MIPS wrapper.
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* (see "Firmware virtual layout and remap configuration" section below)
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*/
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#define ROGUE_MIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2)
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#define ROGUE_MIPSFW_TRAMPOLINE_NUMPAGES BIT(ROGUE_MIPSFW_TRAMPOLINE_LOG2_NUMPAGES)
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#define ROGUE_MIPSFW_TRAMPOLINE_SIZE (ROGUE_MIPSFW_TRAMPOLINE_NUMPAGES << \
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ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
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#define ROGUE_MIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (ROGUE_MIPSFW_TRAMPOLINE_LOG2_NUMPAGES + \
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ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
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#define ROGUE_MIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
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#define ROGUE_MIPSFW_TRAMPOLINE_OFFSET(a) ((a) - ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
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#define ROGUE_MIPSFW_SENSITIVE_ADDR(a) (ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN == \
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(~((1 << ROGUE_MIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE) - 1) \
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& (a)))
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/* Firmware virtual layout and remap configuration. */
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/*
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* For each remap region we define:
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* - the virtual base used by the Firmware to access code/data through that region
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* - the microAptivAP physical address correspondent to the virtual base address,
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* used as input address and remapped to the actual physical address
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* - log2 of size of the region remapped by the MIPS wrapper, i.e. number of bits from
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* the bottom of the base input address that survive onto the output address
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* (this defines both the alignment and the maximum size of the remapped region)
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* - one or more code/data segments within the remapped region.
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*/
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/* Boot remap setup. */
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#define ROGUE_MIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000)
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#define ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000)
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#define ROGUE_MIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12)
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#define ROGUE_MIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (ROGUE_MIPSFW_BOOT_REMAP_VIRTUAL_BASE)
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/* Data remap setup. */
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#define ROGUE_MIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000)
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#define ROGUE_MIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000)
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#define ROGUE_MIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000)
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#define ROGUE_MIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12)
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#define ROGUE_MIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (ROGUE_MIPSFW_DATA_REMAP_VIRTUAL_BASE)
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/* Code remap setup. */
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#define ROGUE_MIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000)
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#define ROGUE_MIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000)
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#define ROGUE_MIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12)
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#define ROGUE_MIPSFW_EXCEPTIONS_VIRTUAL_BASE (ROGUE_MIPSFW_CODE_REMAP_VIRTUAL_BASE)
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/* Permanent mappings setup. */
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#define ROGUE_MIPSFW_PT_VIRTUAL_BASE (0xCF000000)
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#define ROGUE_MIPSFW_REGISTERS_VIRTUAL_BASE (0xCF800000)
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#define ROGUE_MIPSFW_STACK_VIRTUAL_BASE (0xCF600000)
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/* Bootloader configuration data. */
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/*
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* Bootloader configuration offset (where ROGUE_MIPSFW_BOOT_DATA lives)
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* within the bootloader/NMI data page.
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*/
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#define ROGUE_MIPSFW_BOOTLDR_CONF_OFFSET (0x0)
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/* NMI shared data. */
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/* Base address of the shared data within the bootloader/NMI data page. */
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#define ROGUE_MIPSFW_NMI_SHARED_DATA_BASE (0x100)
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/* Size used by Debug dump data. */
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#define ROGUE_MIPSFW_NMI_SHARED_SIZE (0x2B0)
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/* Offsets in the NMI shared area in 32-bit words. */
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#define ROGUE_MIPSFW_NMI_SYNC_FLAG_OFFSET (0x0)
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#define ROGUE_MIPSFW_NMI_STATE_OFFSET (0x1)
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#define ROGUE_MIPSFW_NMI_ERROR_STATE_SET (0x1)
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/* MIPS boot stage. */
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#define ROGUE_MIPSFW_BOOT_STAGE_OFFSET (0x400)
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/*
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* MIPS private data in the bootloader data page.
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* Memory below this offset is used by the FW only, no interface data allowed.
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*/
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#define ROGUE_MIPSFW_PRIVATE_DATA_OFFSET (0x800)
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struct rogue_mipsfw_boot_data {
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u64 stack_phys_addr;
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u64 reg_base;
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u64 pt_phys_addr[ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES];
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u32 pt_log2_page_size;
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u32 pt_num_pages;
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u32 reserved1;
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u32 reserved2;
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};
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#define ROGUE_MIPSFW_GET_OFFSET_IN_DWORDS(offset) ((offset) / sizeof(u32))
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#define ROGUE_MIPSFW_GET_OFFSET_IN_QWORDS(offset) ((offset) / sizeof(u64))
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/* Used for compatibility checks. */
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#define ROGUE_MIPSFW_ARCHTYPE_VER_CLRMSK (0xFFFFE3FFU)
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#define ROGUE_MIPSFW_ARCHTYPE_VER_SHIFT (10U)
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#define ROGUE_MIPSFW_CORE_ID_VALUE (0x001U)
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#define ROGUE_FW_PROCESSOR_MIPS "MIPS"
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/* microAptivAP cache line size. */
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#define ROGUE_MIPSFW_MICROAPTIVEAP_CACHELINE_SIZE (16U)
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/*
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* The SOCIF transactions are identified with the top 16 bits of the physical address emitted by
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* the MIPS.
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*/
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#define ROGUE_MIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN (16U)
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/* Values to put in the MIPS selectors for performance counters. */
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/* Icache accesses in COUNTER0. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ICACHE_ACCESSES_C0 (9U)
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/* Icache misses in COUNTER1. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ICACHE_MISSES_C1 (9U)
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/* Dcache accesses in COUNTER0. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_DCACHE_ACCESSES_C0 (10U)
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/* Dcache misses in COUNTER1. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_DCACHE_MISSES_C1 (11U)
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/* ITLB instruction accesses in COUNTER0. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ITLB_INSTR_ACCESSES_C0 (5U)
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/* JTLB instruction accesses misses in COUNTER1. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_JTLB_INSTR_MISSES_C1 (7U)
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/* Instructions completed in COUNTER0. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_INSTR_COMPLETED_C0 (1U)
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/* JTLB data misses in COUNTER1. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_JTLB_DATA_MISSES_C1 (8U)
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/* Shift for the Event field in the MIPS perf ctrl registers. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_EVENT_SHIFT (5U)
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/* Additional flags for performance counters. See MIPS manual for further reference. */
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_USER_MODE (8U)
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_KERNEL_MODE (2U)
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#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_EXL (1U)
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#define ROGUE_MIPSFW_C0_NBHWIRQ 8
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/* Macros to decode C0_Cause register. */
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#define ROGUE_MIPSFW_C0_CAUSE_EXCCODE(cause) (((cause) & 0x7c) >> 2)
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#define ROGUE_MIPSFW_C0_CAUSE_EXCCODE_FWERROR 9
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/* Use only when Coprocessor Unusable exception. */
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#define ROGUE_MIPSFW_C0_CAUSE_UNUSABLE_UNIT(cause) (((cause) >> 28) & 0x3)
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#define ROGUE_MIPSFW_C0_CAUSE_PENDING_HWIRQ(cause) (((cause) & 0x3fc00) >> 10)
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#define ROGUE_MIPSFW_C0_CAUSE_FDCIPENDING BIT(21)
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#define ROGUE_MIPSFW_C0_CAUSE_IV BIT(23)
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#define ROGUE_MIPSFW_C0_CAUSE_IC BIT(25)
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#define ROGUE_MIPSFW_C0_CAUSE_PCIPENDING BIT(26)
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#define ROGUE_MIPSFW_C0_CAUSE_TIPENDING BIT(30)
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#define ROGUE_MIPSFW_C0_CAUSE_BRANCH_DELAY BIT(31)
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/* Macros to decode C0_Debug register. */
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#define ROGUE_MIPSFW_C0_DEBUG_EXCCODE(debug) (((debug) >> 10) & 0x1f)
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#define ROGUE_MIPSFW_C0_DEBUG_DSS BIT(0)
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#define ROGUE_MIPSFW_C0_DEBUG_DBP BIT(1)
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#define ROGUE_MIPSFW_C0_DEBUG_DDBL BIT(2)
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#define ROGUE_MIPSFW_C0_DEBUG_DDBS BIT(3)
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#define ROGUE_MIPSFW_C0_DEBUG_DIB BIT(4)
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#define ROGUE_MIPSFW_C0_DEBUG_DINT BIT(5)
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#define ROGUE_MIPSFW_C0_DEBUG_DIBIMPR BIT(6)
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#define ROGUE_MIPSFW_C0_DEBUG_DDBLIMPR BIT(18)
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#define ROGUE_MIPSFW_C0_DEBUG_DDBSIMPR BIT(19)
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#define ROGUE_MIPSFW_C0_DEBUG_IEXI BIT(20)
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#define ROGUE_MIPSFW_C0_DEBUG_DBUSEP BIT(21)
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#define ROGUE_MIPSFW_C0_DEBUG_CACHEEP BIT(22)
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#define ROGUE_MIPSFW_C0_DEBUG_MCHECKP BIT(23)
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#define ROGUE_MIPSFW_C0_DEBUG_IBUSEP BIT(24)
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#define ROGUE_MIPSFW_C0_DEBUG_DM BIT(30)
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#define ROGUE_MIPSFW_C0_DEBUG_DBD BIT(31)
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/* Macros to decode TLB entries. */
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#define ROGUE_MIPSFW_TLB_GET_MASK(page_mask) (((page_mask) >> 13) & 0XFFFFU)
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/* Page size in KB. */
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#define ROGUE_MIPSFW_TLB_GET_PAGE_SIZE(page_mask) ((((page_mask) | 0x1FFF) + 1) >> 11)
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/* Page size in KB. */
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#define ROGUE_MIPSFW_TLB_GET_PAGE_MASK(page_size) ((((page_size) << 11) - 1) & ~0x7FF)
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#define ROGUE_MIPSFW_TLB_GET_VPN2(entry_hi) ((entry_hi) >> 13)
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#define ROGUE_MIPSFW_TLB_GET_COHERENCY(entry_lo) (((entry_lo) >> 3) & 0x7U)
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#define ROGUE_MIPSFW_TLB_GET_PFN(entry_lo) (((entry_lo) >> 6) & 0XFFFFFU)
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/* GET_PA uses a non-standard PFN mask for 36 bit addresses. */
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#define ROGUE_MIPSFW_TLB_GET_PA(entry_lo) (((u64)(entry_lo) & \
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ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT) << 6)
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#define ROGUE_MIPSFW_TLB_GET_INHIBIT(entry_lo) (((entry_lo) >> 30) & 0x3U)
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#define ROGUE_MIPSFW_TLB_GET_DGV(entry_lo) ((entry_lo) & 0x7U)
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#define ROGUE_MIPSFW_TLB_GLOBAL BIT(0)
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#define ROGUE_MIPSFW_TLB_VALID BIT(1)
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#define ROGUE_MIPSFW_TLB_DIRTY BIT(2)
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#define ROGUE_MIPSFW_TLB_XI BIT(30)
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#define ROGUE_MIPSFW_TLB_RI BIT(31)
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#define ROGUE_MIPSFW_REMAP_GET_REGION_SIZE(region_size_encoding) (1 << (((region_size_encoding) \
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+ 1) << 1))
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struct rogue_mips_tlb_entry {
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u32 tlb_page_mask;
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u32 tlb_hi;
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u32 tlb_lo0;
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u32 tlb_lo1;
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};
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struct rogue_mips_remap_entry {
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u32 remap_addr_in; /* Always 4k aligned. */
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u32 remap_addr_out; /* Always 4k aligned. */
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u32 remap_region_size;
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};
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struct rogue_mips_state {
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u32 error_state; /* This must come first in the structure. */
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u32 error_epc;
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u32 status_register;
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u32 cause_register;
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u32 bad_register;
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u32 epc;
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u32 sp;
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u32 debug;
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u32 depc;
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u32 bad_instr;
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u32 unmapped_address;
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struct rogue_mips_tlb_entry tlb[ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES];
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struct rogue_mips_remap_entry remap[ROGUE_MIPSFW_NUMBER_OF_REMAP_ENTRIES];
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};
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#include "pvr_rogue_mips_check.h"
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#endif /* PVR_ROGUE_MIPS_H */
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