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1017560164
Christian reports that 4K output using YUV420 encoding fails with the
following error:
Fatal Error, invalid HDMI vclk freq 593406
Modetest shows the following:
3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: xxxx, xxxx,
drm calculated value -------------------------------------^
This indicates that there's a (1kHz) mismatch between the clock
calculated by the drm framework and the meson driver.
Relevant function call stack:
(drm framework)
-> meson_encoder_hdmi_atomic_enable()
-> meson_encoder_hdmi_set_vclk()
-> meson_vclk_setup()
The video clock requested by the drm framework is 593407kHz. This is
passed by meson_encoder_hdmi_atomic_enable() to
meson_encoder_hdmi_set_vclk() and the following formula is applied:
- the frequency is halved (which would be 296703.5kHz) and rounded down
to the next full integer, which is 296703kHz
- TMDS clock is calculated (296703kHz * 10)
- video encoder clock is calculated - this needs to match a table from
meson_vclk.c and so it doubles the previously halved value again
(resulting in 593406kHz)
- meson_vclk_setup() can't find (either directly, or by deriving it from
594000kHz * 1000 / 1001 and rounding to the closest integer value -
which is 593407kHz as originally requested by the drm framework) a
matching clock in it's internal table and errors out with "invalid
HDMI vclk freq"
Fix the division precision by switching the whole meson driver to use
unsigned long long (64-bit) Hz values for clock frequencies instead of
unsigned int (32-bit) kHz to fix the rouding error.
Fixes: e5fab2ec9c ("drm/meson: vclk: add support for YUV420 setup")
Reported-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250421201300.778955-3-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250421201300.778955-3-martin.blumenstingl@googlemail.com
37 lines
950 B
C
37 lines
950 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/* Video Clock */
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#ifndef __MESON_VCLK_H
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#define __MESON_VCLK_H
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#include <drm/drm_modes.h>
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struct meson_drm;
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enum {
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MESON_VCLK_TARGET_CVBS = 0,
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MESON_VCLK_TARGET_HDMI = 1,
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MESON_VCLK_TARGET_DMT = 2,
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};
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/* 27MHz is the CVBS Pixel Clock */
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#define MESON_VCLK_CVBS (27 * 1000 * 1000)
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enum drm_mode_status
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meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned long long freq);
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enum drm_mode_status
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meson_vclk_vic_supported_freq(struct meson_drm *priv,
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unsigned long long phy_freq,
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unsigned long long vclk_freq);
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void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
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unsigned long long phy_freq, unsigned long long vclk_freq,
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unsigned long long venc_freq, unsigned long long dac_freq,
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bool hdmi_use_enci);
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#endif /* __MESON_VCLK_H */
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