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a88fee2d67
smatch reports:
drivers/gpu/drm/omapdrm/dss/base.c:176 omapdss_device_disconnect() error: we previously assumed 'src' could be null (see line 169)
This code is mostly from a time when omapdrm had its own display device
model. I can't honestly remember the details, and I don't think it's
worth digging in deeply into that for a legacy driver.
However, it looks like we only call omapdss_device_disconnect() and
omapdss_device_connect() with NULL as the src parameter. We can thus
drop the src parameter from both functions, and fix the smatch warning.
I don't think omapdss_device_disconnect() ever gets NULL for the dst
parameter (if it did, we'd crash soon after returning from the
function), but I have kept the !dst check, just in case, but I added a
WARN_ON() there.
Also, if the dst parameter can be NULL, we can't always get the struct
dss_device pointer from dst->dss (which is only used for a debug print).
To make sure we can't hit that issue, do it similarly to the
omapdss_device_connect() function: add 'struct dss_device *dss' as the
first parameter, so that we always have it regardless of the dst.
Fixes: 79107f274b ("drm/omap: Add support for drm_bridge")
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240806-omapdrm-misc-fixes-v1-1-15d31aea0831@ideasonboard.com
316 lines
8.5 KiB
C
316 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#ifndef __OMAP_DRM_DSS_H
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#define __OMAP_DRM_DSS_H
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#include <drm/drm_color_mgmt.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_mode.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/platform_data/omapdss.h>
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#include <video/videomode.h>
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#define DISPC_IRQ_FRAMEDONE (1 << 0)
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#define DISPC_IRQ_VSYNC (1 << 1)
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#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
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#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
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#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
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#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
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#define DISPC_IRQ_GFX_END_WIN (1 << 7)
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#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
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#define DISPC_IRQ_OCP_ERR (1 << 9)
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#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
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#define DISPC_IRQ_VID1_END_WIN (1 << 11)
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#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
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#define DISPC_IRQ_VID2_END_WIN (1 << 13)
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#define DISPC_IRQ_SYNC_LOST (1 << 14)
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#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
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#define DISPC_IRQ_WAKEUP (1 << 16)
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#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
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#define DISPC_IRQ_VSYNC2 (1 << 18)
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#define DISPC_IRQ_VID3_END_WIN (1 << 19)
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#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
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#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
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#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
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#define DISPC_IRQ_FRAMEDONETV (1 << 24)
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#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
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#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
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#define DISPC_IRQ_VSYNC3 (1 << 28)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
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#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
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struct dispc_device;
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struct drm_connector;
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struct dss_device;
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struct dss_lcd_mgr_config;
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struct hdmi_avi_infoframe;
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struct omap_drm_private;
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struct omap_dss_device;
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struct snd_aes_iec958;
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struct snd_cea_861_aud_if;
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enum omap_display_type {
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OMAP_DISPLAY_TYPE_NONE = 0,
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OMAP_DISPLAY_TYPE_DPI = 1 << 0,
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OMAP_DISPLAY_TYPE_DBI = 1 << 1,
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OMAP_DISPLAY_TYPE_SDI = 1 << 2,
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OMAP_DISPLAY_TYPE_DSI = 1 << 3,
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OMAP_DISPLAY_TYPE_VENC = 1 << 4,
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OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
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OMAP_DISPLAY_TYPE_DVI = 1 << 6,
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};
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enum omap_plane_id {
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OMAP_DSS_GFX = 0,
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OMAP_DSS_VIDEO1 = 1,
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OMAP_DSS_VIDEO2 = 2,
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OMAP_DSS_VIDEO3 = 3,
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OMAP_DSS_WB = 4,
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};
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enum omap_channel {
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OMAP_DSS_CHANNEL_LCD = 0,
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OMAP_DSS_CHANNEL_DIGIT = 1,
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OMAP_DSS_CHANNEL_LCD2 = 2,
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OMAP_DSS_CHANNEL_LCD3 = 3,
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OMAP_DSS_CHANNEL_WB = 4,
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};
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enum omap_color_mode {
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_UNUSED_,
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};
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enum omap_dss_load_mode {
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OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
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OMAP_DSS_LOAD_CLUT_ONLY = 1,
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OMAP_DSS_LOAD_FRAME_ONLY = 2,
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OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
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};
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enum omap_dss_trans_key_type {
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OMAP_DSS_COLOR_KEY_GFX_DST = 0,
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OMAP_DSS_COLOR_KEY_VID_SRC = 1,
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};
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enum omap_dss_signal_level {
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OMAPDSS_SIG_ACTIVE_LOW,
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OMAPDSS_SIG_ACTIVE_HIGH,
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};
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enum omap_dss_signal_edge {
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OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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OMAPDSS_DRIVE_SIG_RISING_EDGE,
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};
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enum omap_dss_venc_type {
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OMAP_DSS_VENC_TYPE_COMPOSITE,
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OMAP_DSS_VENC_TYPE_SVIDEO,
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};
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enum omap_dss_rotation_type {
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OMAP_DSS_ROT_NONE = 0,
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OMAP_DSS_ROT_TILER = 1 << 0,
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};
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enum omap_overlay_caps {
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OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
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OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
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OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
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OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
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OMAP_DSS_OVL_CAP_POS = 1 << 4,
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OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
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};
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enum omap_dss_output_id {
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OMAP_DSS_OUTPUT_DPI = 1 << 0,
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OMAP_DSS_OUTPUT_DBI = 1 << 1,
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OMAP_DSS_OUTPUT_SDI = 1 << 2,
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OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
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OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
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OMAP_DSS_OUTPUT_VENC = 1 << 5,
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OMAP_DSS_OUTPUT_HDMI = 1 << 6,
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};
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struct omap_dss_cpr_coefs {
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s16 rr, rg, rb;
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s16 gr, gg, gb;
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s16 br, bg, bb;
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};
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struct omap_overlay_info {
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dma_addr_t paddr;
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dma_addr_t p_uv_addr; /* for NV12 format */
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u16 screen_width;
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u16 width;
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u16 height;
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u32 fourcc;
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u8 rotation;
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enum omap_dss_rotation_type rotation_type;
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u16 pos_x;
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u16 pos_y;
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u16 out_width; /* if 0, out_width == width */
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u16 out_height; /* if 0, out_height == height */
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u8 global_alpha;
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u8 pre_mult_alpha;
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u8 zorder;
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enum drm_color_encoding color_encoding;
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enum drm_color_range color_range;
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};
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struct omap_overlay_manager_info {
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u32 default_color;
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enum omap_dss_trans_key_type trans_key_type;
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u32 trans_key;
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bool trans_enabled;
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bool partial_alpha_enabled;
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bool cpr_enable;
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struct omap_dss_cpr_coefs cpr_coefs;
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};
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struct omap_dss_writeback_info {
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u32 paddr;
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u32 p_uv_addr;
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u16 buf_width;
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u16 width;
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u16 height;
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u32 fourcc;
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u8 rotation;
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enum omap_dss_rotation_type rotation_type;
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u8 pre_mult_alpha;
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};
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struct omapdss_dsi_ops {
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int (*update)(struct omap_dss_device *dssdev);
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bool (*is_video_mode)(struct omap_dss_device *dssdev);
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};
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struct omap_dss_device {
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struct device *dev;
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struct dss_device *dss;
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struct drm_bridge *bridge;
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struct drm_bridge *next_bridge;
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struct drm_panel *panel;
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struct list_head list;
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/*
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* DSS type that this device generates (for DSS internal devices) or
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* requires (for external encoders, connectors and panels). Must be a
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* non-zero (different than OMAP_DISPLAY_TYPE_NONE) value.
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*/
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enum omap_display_type type;
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const char *name;
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const struct omapdss_dsi_ops *dsi_ops;
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u32 bus_flags;
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/* OMAP DSS output specific fields */
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/* DISPC channel for this output */
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enum omap_channel dispc_channel;
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/* output instance */
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enum omap_dss_output_id id;
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/* port number in DT */
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unsigned int of_port;
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};
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struct dss_pdata {
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struct dss_device *dss;
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};
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void omapdss_device_register(struct omap_dss_device *dssdev);
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void omapdss_device_unregister(struct omap_dss_device *dssdev);
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struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
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void omapdss_device_put(struct omap_dss_device *dssdev);
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struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
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int omapdss_device_connect(struct dss_device *dss,
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struct omap_dss_device *dst);
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void omapdss_device_disconnect(struct dss_device *dss,
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struct omap_dss_device *dst);
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int omap_dss_get_num_overlay_managers(void);
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int omap_dss_get_num_overlays(void);
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#define for_each_dss_output(d) \
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while ((d = omapdss_device_next_output(d)) != NULL)
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struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
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int omapdss_device_init_output(struct omap_dss_device *out,
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struct drm_bridge *local_bridge);
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void omapdss_device_cleanup_output(struct omap_dss_device *out);
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typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
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int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
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int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
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int omapdss_compat_init(void);
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void omapdss_compat_uninit(void);
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enum dss_writeback_channel {
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DSS_WB_LCD1_MGR = 0,
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DSS_WB_LCD2_MGR = 1,
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DSS_WB_TV_MGR = 2,
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DSS_WB_OVL0 = 3,
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DSS_WB_OVL1 = 4,
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DSS_WB_OVL2 = 5,
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DSS_WB_OVL3 = 6,
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DSS_WB_LCD3_MGR = 7,
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};
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void omap_crtc_dss_start_update(struct omap_drm_private *priv,
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enum omap_channel channel);
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void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable);
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int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel);
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void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel);
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void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
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enum omap_channel channel,
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const struct videomode *vm);
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void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
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enum omap_channel channel,
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const struct dss_lcd_mgr_config *config);
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int omap_crtc_dss_register_framedone(
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struct omap_drm_private *priv, enum omap_channel channel,
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void (*handler)(void *), void *data);
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void omap_crtc_dss_unregister_framedone(
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struct omap_drm_private *priv, enum omap_channel channel,
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void (*handler)(void *), void *data);
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void dss_mgr_set_timings(struct omap_dss_device *dssdev,
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const struct videomode *vm);
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void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
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const struct dss_lcd_mgr_config *config);
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int dss_mgr_enable(struct omap_dss_device *dssdev);
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void dss_mgr_disable(struct omap_dss_device *dssdev);
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void dss_mgr_start_update(struct omap_dss_device *dssdev);
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int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
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void (*handler)(void *), void *data);
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void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
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void (*handler)(void *), void *data);
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struct dispc_device *dispc_get_dispc(struct dss_device *dss);
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bool omapdss_stack_is_ready(void);
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void omapdss_gather_components(struct device *dev);
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int omap_dss_init(void);
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void omap_dss_exit(void);
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#endif /* __OMAP_DRM_DSS_H */
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