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Handle LVDS pixel clock. The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Acked-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-8-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics SA 2017
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*
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* Authors: Philippe Cornu <philippe.cornu@st.com>
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* Yannick Fertre <yannick.fertre@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* Mickael Reulier <mickael.reulier@st.com>
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*/
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#ifndef _LTDC_H_
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#define _LTDC_H_
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struct ltdc_caps {
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u32 hw_version; /* hardware version */
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u32 nb_layers; /* number of supported layers */
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u32 layer_ofs; /* layer offset for applicable regs */
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const u32 *layer_regs; /* layer register offset */
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u32 bus_width; /* bus width (32 or 64 bits) */
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const u32 *pix_fmt_hw; /* supported hw pixel formats */
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const u32 *pix_fmt_drm; /* supported drm pixel formats */
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int pix_fmt_nb; /* number of pixel format */
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bool pix_fmt_flex; /* pixel format flexibility supported */
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bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
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int pad_max_freq_hz; /* max frequency supported by pad */
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int nb_irq; /* number of hardware interrupts */
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bool ycbcr_input; /* ycbcr input converter supported */
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bool ycbcr_output; /* ycbcr output converter supported */
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bool plane_reg_shadow; /* plane shadow registers ability */
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bool crc; /* cyclic redundancy check supported */
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bool dynamic_zorder; /* dynamic z-order */
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bool plane_rotation; /* plane rotation */
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bool fifo_threshold; /* fifo underrun threshold supported */
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};
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#define LTDC_MAX_LAYER 4
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struct fps_info {
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unsigned int counter;
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ktime_t last_timestamp;
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};
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struct ltdc_plat_data {
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int pad_max_freq_hz; /* max frequency supported by pad */
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};
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struct ltdc_device {
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void __iomem *regs;
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struct regmap *regmap;
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struct clk *pixel_clk; /* lcd pixel clock */
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struct clk *lvds_clk; /* lvds pixel clock */
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struct clk *bus_clk; /* bus clock */
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struct mutex err_lock; /* protecting error_status */
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struct ltdc_caps caps;
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u32 irq_status;
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u32 fifo_err; /* fifo underrun error counter */
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u32 fifo_warn; /* fifo underrun warning counter */
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u32 fifo_threshold; /* fifo underrun threshold */
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u32 transfer_err; /* transfer error counter */
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struct fps_info plane_fpsi[LTDC_MAX_LAYER];
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struct drm_atomic_state *suspend_state;
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int crc_skip_count;
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bool crc_active;
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};
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int ltdc_load(struct drm_device *ddev);
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void ltdc_unload(struct drm_device *ddev);
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void ltdc_suspend(struct drm_device *ddev);
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int ltdc_resume(struct drm_device *ddev);
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#endif
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