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Add a Rust driver for ARM Mali CSF-based GPUs. It is a port of Panthor and therefore exposes Panthor's uAPI and name to userspace, and the product of a joint effort between Collabora, Arm and Google engineers. The aim is to incrementally develop Tyr with the abstractions that are currently available until it is consider to be in parity with Panthor feature-wise. The development of Tyr itself started in January, after a few failed attempts of converting Panthor piecewise through a mix of Rust and C code. There is a downstream branch that's much further ahead in terms of capabilities than this initial patch. The downstream code is capable of booting the MCU, doing sync VM_BINDS through the work-in-progress GPUVM abstraction and also doing (trivial) submits through Asahi's drm_scheduler and dma_fence abstractions. So basically, most of what one would expect a modern GPU driver to do, except for power management and some other very important adjacent pieces. It is not at the point where submits can correctly deal with dependencies, or at the point where it can rotate access to the GPU hardware fairly through a software scheduler, but that is simply a matter of writing more code. This first patch, however, only implements a subset of the current features available downstream, as the rest is not implementable without pulling in even more abstractions. In particular, a lot of things depend on properly mapping memory on a given VA range, which itself depends on the GPUVM abstraction that is currently work-in-progress. For this reason, we still cannot boot the MCU and thus, cannot do much for the moment. This constitutes a change in the overall strategy that we have been using to develop Tyr so far. By submitting small parts of the driver upstream iteratively, we aim to: a) evolve together with Nova and rvkms, hopefully reducing regressions due to upstream changes (that may break us because we were not there, in the first place) b) prove any work-in-progress abstractions by having them run on a real driver and hardware and, c) provide a reason to work on and review said abstractions by providing a user, which would be tyr itself. Despite its limited feature-set, we offer IGT tests. It is only tested on the rk3588, so any other SoC is probably not going to work at all for now. The skeleton is basically taken from Nova and also rust_platform_driver.rs. Lastly, the name "Tyr" is inspired by Norse mythology, reflecting ARM's tradition of naming their GPUs after Nordic mythological figures and places. Co-developed-by: Beata Michalska <beata.michalska@arm.com> Signed-off-by: Beata Michalska <beata.michalska@arm.com> Co-developed-by: Carsten Haitzler <carsten.haitzler@foss.arm.com> Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com> Co-developed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://www.collabora.com/news-and-blog/news-and-events/introducing-tyr-a-new-rust-drm-driver.html Signed-off-by: Daniel Almeida <daniel.almeida@collabora.com> Acked-by: Boris Brezillon <boris.brezillon@collabora.com> [aliceryhl: minor Kconfig update on apply] [aliceryhl: s/drm::device::/drm::/] Link: https://lore.kernel.org/r/20250910-tyr-v3-1-dba3bc2ae623@collabora.com Co-developed-by: Alice Ryhl <aliceryhl@google.com> Signed-off-by: Alice Ryhl <aliceryhl@google.com>
108 lines
4.7 KiB
Rust
108 lines
4.7 KiB
Rust
// SPDX-License-Identifier: GPL-2.0 or MIT
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// We don't expect that all the registers and fields will be used, even in the
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// future.
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//
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// Nevertheless, it is useful to have most of them defined, like the C driver
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// does.
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#![allow(dead_code)]
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use kernel::bits::bit_u32;
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use kernel::device::Bound;
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use kernel::device::Device;
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use kernel::devres::Devres;
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use kernel::prelude::*;
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use crate::driver::IoMem;
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/// Represents a register in the Register Set
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///
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/// TODO: Replace this with the Nova `register!()` macro when it is available.
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/// In particular, this will automatically give us 64bit register reads and
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/// writes.
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pub(crate) struct Register<const OFFSET: usize>;
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impl<const OFFSET: usize> Register<OFFSET> {
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#[inline]
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pub(crate) fn read(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<u32> {
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let value = (*iomem).access(dev)?.read32(OFFSET);
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Ok(value)
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}
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#[inline]
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pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u32) -> Result {
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(*iomem).access(dev)?.write32(value, OFFSET);
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Ok(())
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}
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}
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pub(crate) const GPU_ID: Register<0x0> = Register;
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pub(crate) const GPU_L2_FEATURES: Register<0x4> = Register;
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pub(crate) const GPU_CORE_FEATURES: Register<0x8> = Register;
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pub(crate) const GPU_CSF_ID: Register<0x1c> = Register;
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pub(crate) const GPU_REVID: Register<0x280> = Register;
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pub(crate) const GPU_TILER_FEATURES: Register<0xc> = Register;
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pub(crate) const GPU_MEM_FEATURES: Register<0x10> = Register;
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pub(crate) const GPU_MMU_FEATURES: Register<0x14> = Register;
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pub(crate) const GPU_AS_PRESENT: Register<0x18> = Register;
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pub(crate) const GPU_IRQ_RAWSTAT: Register<0x20> = Register;
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pub(crate) const GPU_IRQ_RAWSTAT_FAULT: u32 = bit_u32(0);
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pub(crate) const GPU_IRQ_RAWSTAT_PROTECTED_FAULT: u32 = bit_u32(1);
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pub(crate) const GPU_IRQ_RAWSTAT_RESET_COMPLETED: u32 = bit_u32(8);
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pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE: u32 = bit_u32(9);
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pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL: u32 = bit_u32(10);
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pub(crate) const GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED: u32 = bit_u32(17);
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pub(crate) const GPU_IRQ_RAWSTAT_DOORBELL_STATUS: u32 = bit_u32(18);
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pub(crate) const GPU_IRQ_RAWSTAT_MCU_STATUS: u32 = bit_u32(19);
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pub(crate) const GPU_IRQ_CLEAR: Register<0x24> = Register;
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pub(crate) const GPU_IRQ_MASK: Register<0x28> = Register;
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pub(crate) const GPU_IRQ_STAT: Register<0x2c> = Register;
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pub(crate) const GPU_CMD: Register<0x30> = Register;
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pub(crate) const GPU_CMD_SOFT_RESET: u32 = 1 | (1 << 8);
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pub(crate) const GPU_CMD_HARD_RESET: u32 = 1 | (2 << 8);
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pub(crate) const GPU_THREAD_FEATURES: Register<0xac> = Register;
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pub(crate) const GPU_THREAD_MAX_THREADS: Register<0xa0> = Register;
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pub(crate) const GPU_THREAD_MAX_WORKGROUP_SIZE: Register<0xa4> = Register;
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pub(crate) const GPU_THREAD_MAX_BARRIER_SIZE: Register<0xa8> = Register;
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pub(crate) const GPU_TEXTURE_FEATURES0: Register<0xb0> = Register;
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pub(crate) const GPU_SHADER_PRESENT_LO: Register<0x100> = Register;
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pub(crate) const GPU_SHADER_PRESENT_HI: Register<0x104> = Register;
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pub(crate) const GPU_TILER_PRESENT_LO: Register<0x110> = Register;
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pub(crate) const GPU_TILER_PRESENT_HI: Register<0x114> = Register;
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pub(crate) const GPU_L2_PRESENT_LO: Register<0x120> = Register;
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pub(crate) const GPU_L2_PRESENT_HI: Register<0x124> = Register;
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pub(crate) const L2_READY_LO: Register<0x160> = Register;
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pub(crate) const L2_READY_HI: Register<0x164> = Register;
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pub(crate) const L2_PWRON_LO: Register<0x1a0> = Register;
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pub(crate) const L2_PWRON_HI: Register<0x1a4> = Register;
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pub(crate) const L2_PWRTRANS_LO: Register<0x220> = Register;
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pub(crate) const L2_PWRTRANS_HI: Register<0x204> = Register;
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pub(crate) const L2_PWRACTIVE_LO: Register<0x260> = Register;
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pub(crate) const L2_PWRACTIVE_HI: Register<0x264> = Register;
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pub(crate) const MCU_CONTROL: Register<0x700> = Register;
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pub(crate) const MCU_CONTROL_ENABLE: u32 = 1;
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pub(crate) const MCU_CONTROL_AUTO: u32 = 2;
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pub(crate) const MCU_CONTROL_DISABLE: u32 = 0;
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pub(crate) const MCU_STATUS: Register<0x704> = Register;
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pub(crate) const MCU_STATUS_DISABLED: u32 = 0;
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pub(crate) const MCU_STATUS_ENABLED: u32 = 1;
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pub(crate) const MCU_STATUS_HALT: u32 = 2;
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pub(crate) const MCU_STATUS_FATAL: u32 = 3;
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pub(crate) const GPU_COHERENCY_FEATURES: Register<0x300> = Register;
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pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register;
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pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register;
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pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register;
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pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register;
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pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31);
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pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register;
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pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register;
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pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register;
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pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register;
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