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79aad29c7d
On Tegra186+, the syncpoint ID has 10 bits of space. To allow
using more than 256 syncpoints, fix the mask.
Fixes: 9abdd497cd ("gpu: host1x: Tegra234 device data and headers")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
181 lines
5.5 KiB
C
181 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018 NVIDIA Corporation.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef HOST1X_HW_HOST1X07_UCLASS_H
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#define HOST1X_HW_HOST1X07_UCLASS_H
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static inline u32 host1x_uclass_incr_syncpt_r(void)
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{
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return 0x0;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT \
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host1x_uclass_incr_syncpt_r()
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static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
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{
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return (v & 0xff) << 10;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
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host1x_uclass_incr_syncpt_cond_f(v)
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static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
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{
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return (v & 0x3ff) << 0;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
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host1x_uclass_incr_syncpt_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_r(void)
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{
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return 0x8;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT \
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host1x_uclass_wait_syncpt_r()
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static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
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host1x_uclass_wait_syncpt_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
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host1x_uclass_wait_syncpt_thresh_f(v)
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static inline u32 host1x_uclass_wait_syncpt_base_r(void)
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{
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return 0x9;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
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host1x_uclass_wait_syncpt_base_r()
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static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
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host1x_uclass_wait_syncpt_base_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
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{
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return (v & 0xff) << 16;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
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host1x_uclass_wait_syncpt_base_base_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
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{
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return (v & 0xffff) << 0;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
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host1x_uclass_wait_syncpt_base_offset_f(v)
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static inline u32 host1x_uclass_load_syncpt_base_r(void)
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{
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return 0xb;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
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host1x_uclass_load_syncpt_base_r()
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static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
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host1x_uclass_load_syncpt_base_base_indx_f(v)
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static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
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host1x_uclass_load_syncpt_base_value_f(v)
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static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
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host1x_uclass_incr_syncpt_base_base_indx_f(v)
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static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
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host1x_uclass_incr_syncpt_base_offset_f(v)
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static inline u32 host1x_uclass_indoff_r(void)
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{
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return 0x2d;
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}
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#define HOST1X_UCLASS_INDOFF \
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host1x_uclass_indoff_r()
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static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
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{
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return (v & 0xf) << 28;
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}
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#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
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host1x_uclass_indoff_indbe_f(v)
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static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
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{
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return (v & 0x1) << 27;
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}
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#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
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host1x_uclass_indoff_autoinc_f(v)
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static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
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{
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return (v & 0xff) << 18;
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}
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#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
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host1x_uclass_indoff_indmodid_f(v)
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static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
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{
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return (v & 0xffff) << 2;
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}
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#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
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host1x_uclass_indoff_indroffset_f(v)
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static inline u32 host1x_uclass_indoff_rwn_read_v(void)
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{
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return 1;
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}
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#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
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host1x_uclass_indoff_indroffset_f(v)
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static inline u32 host1x_uclass_load_syncpt_payload_32_r(void)
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{
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return 0x4e;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \
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host1x_uclass_load_syncpt_payload_32_r()
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static inline u32 host1x_uclass_wait_syncpt_32_r(void)
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{
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return 0x50;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_32 \
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host1x_uclass_wait_syncpt_32_r()
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#endif
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