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151f3d29ba
Add driver to configure the STM32MP25 SoC PCIe controller based on the DesignWare PCIe core in endpoint mode. Controller support 2.5 and 5 GT/s data rates and uses the common reference clock provided by the host. The PCIe core_clk receives the pipe0_clk from the ComboPHY as input, and the ComboPHY PLL must be locked for pipe0_clk to be ready. Consequently, PCIe core registers cannot be accessed until the ComboPHY is fully initialised and REFCLK is enabled and ready. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> [mani: reworded description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: squash in https://patch.msgid.link/20250902122641.269725-1-christian.bruel@foss.st.com to remove redundant link_status checks] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250820075411.1178729-7-christian.bruel@foss.st.com
16 lines
467 B
C
16 lines
467 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ST PCIe driver definitions for STM32-MP25 SoC
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*
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* Copyright (C) 2025 STMicroelectronics - All Rights Reserved
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* Author: Christian Bruel <christian.bruel@foss.st.com>
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*/
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#define to_stm32_pcie(x) dev_get_drvdata((x)->dev)
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#define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8)
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#define STM32MP25_PCIECR_EP 0
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#define STM32MP25_PCIECR_LTSSM_EN BIT(2)
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#define STM32MP25_PCIECR_RC BIT(10)
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#define SYSCFG_PCIECR 0x6000
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