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07bab7b81d
Declare the positional index for the RP1 MIPI clocks. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/c20066500908db854aa4816b40e956296bab526a.1750714412.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
65 lines
1.6 KiB
C
65 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2021 Raspberry Pi Ltd.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
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#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
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#define RP1_PLL_SYS_CORE 0
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#define RP1_PLL_AUDIO_CORE 1
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#define RP1_PLL_VIDEO_CORE 2
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#define RP1_PLL_SYS 3
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#define RP1_PLL_AUDIO 4
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#define RP1_PLL_VIDEO 5
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#define RP1_PLL_SYS_PRI_PH 6
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#define RP1_PLL_SYS_SEC_PH 7
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#define RP1_PLL_AUDIO_PRI_PH 8
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#define RP1_PLL_SYS_SEC 9
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#define RP1_PLL_AUDIO_SEC 10
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#define RP1_PLL_VIDEO_SEC 11
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#define RP1_CLK_SYS 12
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#define RP1_CLK_SLOW_SYS 13
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#define RP1_CLK_DMA 14
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#define RP1_CLK_UART 15
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#define RP1_CLK_ETH 16
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#define RP1_CLK_PWM0 17
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#define RP1_CLK_PWM1 18
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#define RP1_CLK_AUDIO_IN 19
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#define RP1_CLK_AUDIO_OUT 20
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#define RP1_CLK_I2S 21
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#define RP1_CLK_MIPI0_CFG 22
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#define RP1_CLK_MIPI1_CFG 23
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#define RP1_CLK_PCIE_AUX 24
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#define RP1_CLK_USBH0_MICROFRAME 25
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#define RP1_CLK_USBH1_MICROFRAME 26
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#define RP1_CLK_USBH0_SUSPEND 27
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#define RP1_CLK_USBH1_SUSPEND 28
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#define RP1_CLK_ETH_TSU 29
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#define RP1_CLK_ADC 30
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#define RP1_CLK_SDIO_TIMER 31
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#define RP1_CLK_SDIO_ALT_SRC 32
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#define RP1_CLK_GP0 33
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#define RP1_CLK_GP1 34
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#define RP1_CLK_GP2 35
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#define RP1_CLK_GP3 36
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#define RP1_CLK_GP4 37
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#define RP1_CLK_GP5 38
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#define RP1_CLK_VEC 39
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#define RP1_CLK_DPI 40
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#define RP1_CLK_MIPI0_DPI 41
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#define RP1_CLK_MIPI1_DPI 42
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/* Extra PLL output channels - RP1B0 only */
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#define RP1_PLL_VIDEO_PRI_PH 43
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#define RP1_PLL_AUDIO_TERN 44
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/* MIPI clocks managed by the DSI driver */
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#define RP1_CLK_MIPI0_DSI_BYTECLOCK 45
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#define RP1_CLK_MIPI1_DSI_BYTECLOCK 46
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#endif
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