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The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
24 lines
540 B
C
24 lines
540 B
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Qualcomm QMP PHY constants
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*
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* Copyright (C) 2022 Linaro Limited
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*/
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#ifndef _DT_BINDINGS_PHY_QMP
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#define _DT_BINDINGS_PHY_QMP
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/* QMP USB4-USB3-DP clocks */
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#define QMP_USB43DP_USB3_PIPE_CLK 0
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#define QMP_USB43DP_DP_LINK_CLK 1
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#define QMP_USB43DP_DP_VCO_DIV_CLK 2
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/* QMP USB4-USB3-DP PHYs */
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#define QMP_USB43DP_USB3_PHY 0
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#define QMP_USB43DP_DP_PHY 1
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/* QMP PCIE PHYs */
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#define QMP_PCIE_PIPE_CLK 0
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#define QMP_PCIE_PHY_AUX_CLK 1
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#endif /* _DT_BINDINGS_PHY_QMP */
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