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d38ceaf99e
This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
85 lines
3 KiB
C
85 lines
3 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_DPM_H__
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#define __AMDGPU_DPM_H__
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#define R600_SSTU_DFLT 0
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#define R600_SST_DFLT 0x00C8
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/* XXX are these ok? */
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#define R600_TEMP_RANGE_MIN (90 * 1000)
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#define R600_TEMP_RANGE_MAX (120 * 1000)
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#define FDO_PWM_MODE_STATIC 1
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#define FDO_PWM_MODE_STATIC_RPM 5
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enum amdgpu_td {
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AMDGPU_TD_AUTO,
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AMDGPU_TD_UP,
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AMDGPU_TD_DOWN,
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};
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enum amdgpu_display_watermark {
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AMDGPU_DISPLAY_WATERMARK_LOW = 0,
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AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
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};
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enum amdgpu_display_gap
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{
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AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
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AMDGPU_PM_DISPLAY_GAP_VBLANK = 1,
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AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2,
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AMDGPU_PM_DISPLAY_GAP_IGNORE = 3,
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};
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void amdgpu_dpm_print_class_info(u32 class, u32 class2);
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void amdgpu_dpm_print_cap_info(u32 caps);
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void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
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struct amdgpu_ps *rps);
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u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
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u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
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bool amdgpu_is_uvd_state(u32 class, u32 class2);
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void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
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u32 *p, u32 *u);
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int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
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bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
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int amdgpu_get_platform_caps(struct amdgpu_device *adev);
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int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
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void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
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void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
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enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
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u32 sys_mask,
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enum amdgpu_pcie_gen asic_gen,
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enum amdgpu_pcie_gen default_gen);
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u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
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u16 asic_lanes,
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u16 default_lanes);
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u8 amdgpu_encode_pci_lane_width(u32 lanes);
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#endif
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