mirror of
https://github.com/torvalds/linux.git
synced 2025-11-08 04:30:00 +02:00
70ec2e8be7
Turns out the DSB indexed register write command has rather significant initial overhead compared to the normal MMIO write command. Based on some quick experiments on TGL you have to write the register at least ~5 times for the indexed write command to come out ahead. If you write the register less times than that the MMIO write is faster. So it seems my automagic indexed write logic was a bit misguided. Go back to the original approach only use indexed writes for the cases we know will benefit from it (indexed LUT register updates). Currently we shouldn't have any cases where this truly matters (just some rare double writes to the precision LUT index registers), but we will need to switch the legacy LUT updates to write each LUT register twice (to avoid some palette anti-collision logic troubles). This would be close to the worst case for using indexed writes (two writes per register, and 256 separate registers). Using the MMIO write command should shave off around 30% of the execution time compared to using the indexed write command. Cc: stable@vger.kernel.org Fixes:34d8311f4a("drm/i915/dsb: Re-instate DSB for LUT updates") Fixes:25ea3411bd("drm/i915/dsb: Use non-posted register writes for legacy LUT") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120164123.12706-2-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com> (cherry picked from commitecba559a88) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
69 lines
2 KiB
C
69 lines
2 KiB
C
/* SPDX-License-Identifier: MIT
|
|
*
|
|
* Copyright © 2019 Intel Corporation
|
|
*/
|
|
|
|
#ifndef _INTEL_DSB_H
|
|
#define _INTEL_DSB_H
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include "i915_reg_defs.h"
|
|
|
|
struct intel_atomic_state;
|
|
struct intel_crtc;
|
|
struct intel_crtc_state;
|
|
struct intel_display;
|
|
struct intel_dsb;
|
|
|
|
enum pipe;
|
|
|
|
enum intel_dsb_id {
|
|
INTEL_DSB_0,
|
|
INTEL_DSB_1,
|
|
INTEL_DSB_2,
|
|
|
|
I915_MAX_DSBS,
|
|
};
|
|
|
|
struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
|
|
struct intel_crtc *crtc,
|
|
enum intel_dsb_id dsb_id,
|
|
unsigned int max_cmds);
|
|
void intel_dsb_finish(struct intel_dsb *dsb);
|
|
void intel_dsb_cleanup(struct intel_dsb *dsb);
|
|
void intel_dsb_reg_write(struct intel_dsb *dsb,
|
|
i915_reg_t reg, u32 val);
|
|
void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
|
|
i915_reg_t reg, u32 val);
|
|
void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
|
|
i915_reg_t reg, u32 mask, u32 val);
|
|
void intel_dsb_noop(struct intel_dsb *dsb, int count);
|
|
void intel_dsb_nonpost_start(struct intel_dsb *dsb);
|
|
void intel_dsb_nonpost_end(struct intel_dsb *dsb);
|
|
void intel_dsb_interrupt(struct intel_dsb *dsb);
|
|
void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
|
|
void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
|
|
void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
|
|
struct intel_dsb *dsb);
|
|
void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
|
|
struct intel_dsb *dsb,
|
|
int lower, int upper);
|
|
void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
|
|
struct intel_dsb *dsb,
|
|
int lower, int upper);
|
|
void intel_dsb_vblank_evade(struct intel_atomic_state *state,
|
|
struct intel_dsb *dsb);
|
|
void intel_dsb_chain(struct intel_atomic_state *state,
|
|
struct intel_dsb *dsb,
|
|
struct intel_dsb *chained_dsb,
|
|
bool wait_for_vblank);
|
|
|
|
void intel_dsb_commit(struct intel_dsb *dsb,
|
|
bool wait_for_vblank);
|
|
void intel_dsb_wait(struct intel_dsb *dsb);
|
|
|
|
void intel_dsb_irq_handler(struct intel_display *display,
|
|
enum pipe pipe, enum intel_dsb_id dsb_id);
|
|
|
|
#endif
|