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de8f847a51
Add support for DMABUF MR registrations with Data-direct device. Upon userspace calling to register a DMABUF MR with the data direct bit set, the below algorithm will be followed. 1) Obtain a pinned DMABUF umem from the IB core using the user input parameters (FD, offset, length) and the DMA PF device. The DMA PF device is needed to allow the IOMMU to enable the DMA PF to access the user buffer over PCI. 2) Create a KSM MKEY by setting its entries according to the user buffer VA to IOVA mapping, with the MKEY being the data direct device-crossed MKEY. This KSM MKEY is umrable and will be used as part of the MR cache. The PD for creating it is the internal device 'data direct' kernel one. 3) Create a crossing MKEY that points to the KSM MKEY using the crossing access mode. 4) Manage the KSM MKEY by adding it to a list of 'data direct' MKEYs managed on the mlx5_ib device. 5) Return the crossing MKEY to the user, created with its supplied PD. Upon DMA PF unbind flow, the driver will revoke the KSM entries. The final deregistration will occur under the hood once the application deregisters its MKEY. Notes: - This version supports only the PINNED UMEM mode, so there is no dependency on ODP. - The IOVA supplied by the application must be system page aligned due to HW translations of KSM. - The crossing MKEY will not be umrable or part of the MR cache, as we cannot change its crossed (i.e. KSM) MKEY over UMR. Signed-off-by: Yishai Hadas <yishaih@nvidia.com> Link: https://patch.msgid.link/1f99d8020ed540d9702b9e2252a145a439609ba6.1722512548.git.leon@kernel.org Signed-off-by: Leon Romanovsky <leon@kernel.org>
102 lines
3.1 KiB
C
102 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
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#ifndef _MLX5_IB_UMR_H
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#define _MLX5_IB_UMR_H
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#include "mlx5_ib.h"
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#define MLX5_MAX_UMR_SHIFT 16
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#define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
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#define MLX5_IB_UMR_OCTOWORD 16
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#define MLX5_IB_UMR_XLT_ALIGNMENT 64
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int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev);
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void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev);
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int mlx5r_umr_init(struct mlx5_ib_dev *dev);
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void mlx5r_umr_cleanup(struct mlx5_ib_dev *dev);
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static inline bool mlx5r_umr_can_load_pas(struct mlx5_ib_dev *dev,
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size_t length)
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{
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/*
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* umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is
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* always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka
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* MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey
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* can never be enabled without this capability. Simplify this weird
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* quirky hardware by just saying it can't use PAS lists with UMR at
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* all.
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*/
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if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
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return false;
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/*
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* length is the size of the MR in bytes when mlx5_ib_update_xlt() is
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* used.
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*/
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if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) &&
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length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE)
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return false;
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return true;
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}
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/*
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* true if an existing MR can be reconfigured to new access_flags using UMR.
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* Older HW cannot use UMR to update certain elements of the MKC. See
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* get_umr_update_access_mask() and umr_check_mkey_mask()
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*/
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static inline bool mlx5r_umr_can_reconfig(struct mlx5_ib_dev *dev,
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unsigned int current_access_flags,
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unsigned int target_access_flags)
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{
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unsigned int diffs = current_access_flags ^ target_access_flags;
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if ((diffs & IB_ACCESS_REMOTE_ATOMIC) &&
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MLX5_CAP_GEN(dev->mdev, atomic) &&
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MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
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return false;
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if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
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return false;
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if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
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(MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) ||
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
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return false;
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return true;
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}
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static inline u64 mlx5r_umr_get_xlt_octo(u64 bytes)
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{
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return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
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MLX5_IB_UMR_OCTOWORD;
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}
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struct mlx5r_umr_context {
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struct ib_cqe cqe;
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enum ib_wc_status status;
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struct completion done;
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};
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struct mlx5r_umr_wqe {
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struct mlx5_wqe_umr_ctrl_seg ctrl_seg;
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struct mlx5_mkey_seg mkey_seg;
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struct mlx5_wqe_data_seg data_seg;
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};
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int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr);
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int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
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int access_flags);
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int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags);
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int mlx5r_umr_update_data_direct_ksm_pas(struct mlx5_ib_mr *mr, unsigned int flags);
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int mlx5r_umr_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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int page_shift, int flags);
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#endif /* _MLX5_IB_UMR_H */
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