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The latest AMD processors include additional IP blocks that must be turned off before transitioning to low power. PMFW provides an interface to retrieve debug information from each IP block, which is useful for diagnosing issues if the system fails to enter or exit low power states, or for profiling which IP block takes more time. Add support for using this information within the driver. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20241108070822.3912689-8-Shyam-sundar.S-k@amd.com [ij: grouped active_ips, ips_ptr, and num_ips next to each other.] Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
91 lines
2.1 KiB
C
91 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* AMD SoC Power Management Controller Driver
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*
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* Copyright (c) 2023, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Mario Limonciello <mario.limonciello@amd.com>
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*/
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#ifndef PMC_H
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#define PMC_H
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#include <linux/types.h>
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#include <linux/mutex.h>
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enum s2d_msg_port {
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MSG_PORT_PMC,
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MSG_PORT_S2D,
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};
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struct amd_mp2_dev {
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void __iomem *mmio;
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void __iomem *vslbase;
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void *stbdata;
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void *devres_gid;
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struct pci_dev *pdev;
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dma_addr_t dma_addr;
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int stb_len;
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bool is_stb_data;
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};
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struct stb_arg {
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u32 s2d_msg_id;
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u32 msg;
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u32 arg;
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u32 resp;
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};
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struct amd_pmc_dev {
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void __iomem *regbase;
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void __iomem *smu_virt_addr;
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void __iomem *stb_virt_addr;
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void __iomem *fch_virt_addr;
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u32 base_addr;
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u32 cpu_id;
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u32 dram_size;
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u32 active_ips;
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const struct amd_pmc_bit_map *ips_ptr;
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u32 num_ips;
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u32 smu_msg;
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/* SMU version information */
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u8 smu_program;
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u8 major;
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u8 minor;
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u8 rev;
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u8 msg_port;
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struct device *dev;
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struct pci_dev *rdev;
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struct mutex lock; /* generic mutex lock */
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struct dentry *dbgfs_dir;
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struct quirk_entry *quirks;
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bool disable_8042_wakeup;
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struct amd_mp2_dev *mp2;
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struct stb_arg stb_arg;
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};
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void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);
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void amd_pmc_quirks_init(struct amd_pmc_dev *dev);
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void amd_mp2_stb_init(struct amd_pmc_dev *dev);
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void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
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/* List of supported CPU ids */
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#define AMD_CPU_ID_RV 0x15D0
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#define AMD_CPU_ID_RN 0x1630
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#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
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#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
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#define AMD_CPU_ID_YC 0x14B5
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#define AMD_CPU_ID_CB 0x14D8
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#define AMD_CPU_ID_PS 0x14E8
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#define AMD_CPU_ID_SP 0x14A4
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#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
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#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
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#define PCI_DEVICE_ID_AMD_MP2_STB 0x172c
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int amd_stb_s2d_init(struct amd_pmc_dev *dev);
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int amd_stb_read(struct amd_pmc_dev *dev, u32 *buf);
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int amd_stb_write(struct amd_pmc_dev *dev, u32 data);
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int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
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#endif /* PMC_H */
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