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ae6e7e635c
Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7011/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
131 lines
3 KiB
C
131 lines
3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <uapi/asm/bitfield.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#define PCI_CONFIG_ADDRESS 0xcf8
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#define PCI_CONFIG_DATA 0xcfc
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union pci_config_address {
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struct {
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__BITFIELD_FIELD(unsigned enable_bit : 1, /* 31 */
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__BITFIELD_FIELD(unsigned reserved : 7, /* 30 .. 24 */
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__BITFIELD_FIELD(unsigned bus_number : 8, /* 23 .. 16 */
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__BITFIELD_FIELD(unsigned devfn_number : 8, /* 15 .. 8 */
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__BITFIELD_FIELD(unsigned register_number : 8, /* 7 .. 0 */
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)))));
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};
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u32 w;
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};
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return ((pin + slot) % 4)+ MIPS_IRQ_PCIA;
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}
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static void pci_virtio_guest_write_config_addr(struct pci_bus *bus,
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unsigned int devfn, int reg)
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{
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union pci_config_address pca = { .w = 0 };
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pca.register_number = reg;
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pca.devfn_number = devfn;
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pca.bus_number = bus->number;
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pca.enable_bit = 1;
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outl(pca.w, PCI_CONFIG_ADDRESS);
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}
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static int pci_virtio_guest_write_config(struct pci_bus *bus,
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unsigned int devfn, int reg, int size, u32 val)
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{
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pci_virtio_guest_write_config_addr(bus, devfn, reg);
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switch (size) {
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case 1:
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outb(val, PCI_CONFIG_DATA + (reg & 3));
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break;
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case 2:
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outw(val, PCI_CONFIG_DATA + (reg & 2));
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break;
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case 4:
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outl(val, PCI_CONFIG_DATA);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_virtio_guest_read_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 *val)
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{
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pci_virtio_guest_write_config_addr(bus, devfn, reg);
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switch (size) {
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case 1:
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*val = inb(PCI_CONFIG_DATA + (reg & 3));
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break;
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case 2:
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*val = inw(PCI_CONFIG_DATA + (reg & 2));
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break;
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case 4:
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*val = inl(PCI_CONFIG_DATA);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_virtio_guest_ops = {
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.read = pci_virtio_guest_read_config,
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.write = pci_virtio_guest_write_config,
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};
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static struct resource pci_virtio_guest_mem_resource = {
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.name = "Virtio MEM",
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.flags = IORESOURCE_MEM,
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.start = 0x10000000,
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.end = 0x1dffffff
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};
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static struct resource pci_virtio_guest_io_resource = {
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.name = "Virtio IO",
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.flags = IORESOURCE_IO,
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.start = 0,
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.end = 0xffff
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};
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static struct pci_controller pci_virtio_guest_controller = {
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.pci_ops = &pci_virtio_guest_ops,
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.mem_resource = &pci_virtio_guest_mem_resource,
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.io_resource = &pci_virtio_guest_io_resource,
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};
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static int __init pci_virtio_guest_setup(void)
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{
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pr_err("pci_virtio_guest_setup\n");
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/* Virtio comes pre-assigned */
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pci_set_flags(PCI_PROBE_ONLY);
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pci_virtio_guest_controller.io_map_base = mips_io_port_base;
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register_pci_controller(&pci_virtio_guest_controller);
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return 0;
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}
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arch_initcall(pci_virtio_guest_setup);
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