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424268c749
Add support for MT2712 and MT7622. Due to register offset address of pwm7 for MT2712 is not fixed 0x40, add mtk_pwm_reg_offset array for PWM register offset. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
284 lines
6.5 KiB
C
284 lines
6.5 KiB
C
/*
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* Mediatek Pulse Width Modulator driver
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*
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* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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/* PWM registers and bits definitions */
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#define PWMCON 0x00
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#define PWMHDUR 0x04
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#define PWMLDUR 0x08
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#define PWMGDUR 0x0c
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#define PWMWAVENUM 0x28
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#define PWMDWIDTH 0x2c
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#define PWMTHRES 0x30
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#define PWM_CLK_DIV_MAX 7
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enum {
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MTK_CLK_MAIN = 0,
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MTK_CLK_TOP,
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MTK_CLK_PWM1,
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MTK_CLK_PWM2,
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MTK_CLK_PWM3,
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MTK_CLK_PWM4,
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MTK_CLK_PWM5,
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MTK_CLK_PWM6,
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MTK_CLK_PWM7,
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MTK_CLK_PWM8,
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MTK_CLK_MAX,
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};
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static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
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"main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
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"pwm8"
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};
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struct mtk_pwm_platform_data {
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unsigned int num_pwms;
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};
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/**
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* struct mtk_pwm_chip - struct representing PWM chip
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* @chip: linux PWM chip representation
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* @regs: base address of PWM chip
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* @clks: list of clocks
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*/
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struct mtk_pwm_chip {
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struct pwm_chip chip;
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void __iomem *regs;
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struct clk *clks[MTK_CLK_MAX];
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};
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static const unsigned int mtk_pwm_reg_offset[] = {
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0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
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};
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static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct mtk_pwm_chip, chip);
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}
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static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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int ret;
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ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
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if (ret < 0)
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return ret;
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ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
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if (ret < 0)
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goto disable_clk_top;
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ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
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if (ret < 0)
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goto disable_clk_main;
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return 0;
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disable_clk_main:
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clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
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disable_clk_top:
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clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
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return ret;
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}
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static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
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clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
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clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
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}
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static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
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unsigned int offset)
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{
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return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
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}
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static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
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unsigned int num, unsigned int offset,
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u32 value)
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{
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writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
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}
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static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
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u32 resolution, clkdiv = 0;
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int ret;
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ret = mtk_pwm_clk_enable(chip, pwm);
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if (ret < 0)
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return ret;
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resolution = NSEC_PER_SEC / clk_get_rate(clk);
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while (period_ns / resolution > 8191) {
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resolution *= 2;
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clkdiv++;
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}
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if (clkdiv > PWM_CLK_DIV_MAX) {
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mtk_pwm_clk_disable(chip, pwm);
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dev_err(chip->dev, "period %d not supported\n", period_ns);
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return -EINVAL;
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}
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mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
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mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
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mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
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mtk_pwm_clk_disable(chip, pwm);
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return 0;
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}
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static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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u32 value;
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int ret;
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ret = mtk_pwm_clk_enable(chip, pwm);
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if (ret < 0)
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return ret;
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value = readl(pc->regs);
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value |= BIT(pwm->hwpwm);
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writel(value, pc->regs);
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return 0;
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}
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static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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u32 value;
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value = readl(pc->regs);
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value &= ~BIT(pwm->hwpwm);
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writel(value, pc->regs);
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mtk_pwm_clk_disable(chip, pwm);
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}
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static const struct pwm_ops mtk_pwm_ops = {
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.config = mtk_pwm_config,
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.enable = mtk_pwm_enable,
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.disable = mtk_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int mtk_pwm_probe(struct platform_device *pdev)
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{
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const struct mtk_pwm_platform_data *data;
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struct mtk_pwm_chip *pc;
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struct resource *res;
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unsigned int i;
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int ret;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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data = of_device_get_match_data(&pdev->dev);
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if (data == NULL)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pc->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pc->regs))
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return PTR_ERR(pc->regs);
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for (i = 0; i < data->num_pwms + 2; i++) {
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pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
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if (IS_ERR(pc->clks[i])) {
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dev_err(&pdev->dev, "clock: %s fail: %ld\n",
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mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
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return PTR_ERR(pc->clks[i]);
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}
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}
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platform_set_drvdata(pdev, pc);
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &mtk_pwm_ops;
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pc->chip.base = -1;
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pc->chip.npwm = data->num_pwms;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int mtk_pwm_remove(struct platform_device *pdev)
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{
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struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
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return pwmchip_remove(&pc->chip);
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}
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static const struct mtk_pwm_platform_data mt2712_pwm_data = {
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.num_pwms = 8,
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};
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static const struct mtk_pwm_platform_data mt7622_pwm_data = {
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.num_pwms = 6,
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};
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static const struct mtk_pwm_platform_data mt7623_pwm_data = {
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.num_pwms = 5,
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};
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static const struct of_device_id mtk_pwm_of_match[] = {
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{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
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{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
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{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
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{ },
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};
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MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
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static struct platform_driver mtk_pwm_driver = {
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.driver = {
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.name = "mtk-pwm",
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.of_match_table = mtk_pwm_of_match,
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},
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.probe = mtk_pwm_probe,
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.remove = mtk_pwm_remove,
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};
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module_platform_driver(mtk_pwm_driver);
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MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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MODULE_ALIAS("platform:mtk-pwm");
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MODULE_LICENSE("GPL");
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