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142600e854
v1: Aldebaran uses reset control to support mode2 reset. The sequences to reset and restore hardware context are specific to a particular configuration. v2: Clear bus mastering before reset. Fix coding style issues, drop unwanted variables and info log. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_reset.h"
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#include "aldebaran.h"
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int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_handler *handler)
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{
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/* TODO: Check if handler exists? */
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list_add_tail(&handler->handler_list, &reset_ctl->reset_handlers);
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return 0;
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}
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int amdgpu_reset_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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switch (adev->asic_type) {
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case CHIP_ALDEBARAN:
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ret = aldebaran_reset_init(adev);
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break;
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default:
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break;
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}
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return ret;
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}
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int amdgpu_reset_fini(struct amdgpu_device *adev)
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{
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int ret = 0;
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switch (adev->asic_type) {
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case CHIP_ALDEBARAN:
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ret = aldebaran_reset_fini(adev);
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break;
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default:
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break;
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}
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return ret;
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}
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int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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if (!reset_handler)
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return -ENOSYS;
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return reset_handler->prepare_hwcontext(adev->reset_cntl,
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reset_context);
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}
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int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context)
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{
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int ret;
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (adev->reset_cntl)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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if (!reset_handler)
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return -ENOSYS;
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ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
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if (ret)
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return ret;
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return reset_handler->restore_hwcontext(adev->reset_cntl,
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reset_context);
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}
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