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	The FPGA bridge class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code and combines the create() and register() functions into a single register() function. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
		
			
				
	
	
		
			109 lines
		
	
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			109 lines
		
	
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
// SPDX-License-Identifier: GPL-2.0
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/*
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 * FPGA Bridge Driver for FPGA Management Engine (FME)
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 *
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 * Copyright (C) 2017-2018 Intel Corporation, Inc.
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 *
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 * Authors:
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 *   Wu Hao <hao.wu@intel.com>
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 *   Joseph Grecco <joe.grecco@intel.com>
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 *   Enno Luebbers <enno.luebbers@intel.com>
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 *   Tim Whisonant <tim.whisonant@intel.com>
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 *   Ananda Ravuri <ananda.ravuri@intel.com>
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 *   Henry Mitchel <henry.mitchel@intel.com>
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 */
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#include <linux/module.h>
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#include <linux/fpga/fpga-bridge.h>
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#include "dfl.h"
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#include "dfl-fme-pr.h"
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struct fme_br_priv {
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	struct dfl_fme_br_pdata *pdata;
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	struct dfl_fpga_port_ops *port_ops;
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	struct platform_device *port_pdev;
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};
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static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable)
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{
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	struct fme_br_priv *priv = bridge->priv;
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	struct platform_device *port_pdev;
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	struct dfl_fpga_port_ops *ops;
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	if (!priv->port_pdev) {
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		port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev,
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						    &priv->pdata->port_id,
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						    dfl_fpga_check_port_id);
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		if (!port_pdev)
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			return -ENODEV;
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		priv->port_pdev = port_pdev;
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	}
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	if (priv->port_pdev && !priv->port_ops) {
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		ops = dfl_fpga_port_ops_get(priv->port_pdev);
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		if (!ops || !ops->enable_set)
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			return -ENOENT;
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		priv->port_ops = ops;
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	}
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	return priv->port_ops->enable_set(priv->port_pdev, enable);
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}
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static const struct fpga_bridge_ops fme_bridge_ops = {
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	.enable_set = fme_bridge_enable_set,
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};
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static int fme_br_probe(struct platform_device *pdev)
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{
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	struct device *dev = &pdev->dev;
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	struct fme_br_priv *priv;
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	struct fpga_bridge *br;
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	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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	if (!priv)
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		return -ENOMEM;
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	priv->pdata = dev_get_platdata(dev);
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	br = fpga_bridge_register(dev, "DFL FPGA FME Bridge",
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				  &fme_bridge_ops, priv);
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	if (IS_ERR(br))
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		return PTR_ERR(br);
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	platform_set_drvdata(pdev, br);
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	return 0;
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}
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static int fme_br_remove(struct platform_device *pdev)
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{
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	struct fpga_bridge *br = platform_get_drvdata(pdev);
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	struct fme_br_priv *priv = br->priv;
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	fpga_bridge_unregister(br);
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	if (priv->port_pdev)
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		put_device(&priv->port_pdev->dev);
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	if (priv->port_ops)
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		dfl_fpga_port_ops_put(priv->port_ops);
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	return 0;
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}
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static struct platform_driver fme_br_driver = {
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	.driver	= {
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		.name    = DFL_FPGA_FME_BRIDGE,
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	},
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	.probe   = fme_br_probe,
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	.remove  = fme_br_remove,
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};
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module_platform_driver(fme_br_driver);
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MODULE_DESCRIPTION("FPGA Bridge for DFL FPGA Management Engine");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dfl-fme-bridge");
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